DRAM with self-resetting data path for reduced power...

Details DRAM with self-resetting data path for reduced power... DRAM with self-resetting data path for reduced power...

2006-11-14

2006-11-14

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Accelerating charge or discharge

C365S203000, C365S230030

Reexamination Certificate

active

07136317

ABSTRACT:
A random access memory (RAM), such as a dynamic RAM (DRAM) or embedded DRAM (eDRAM) on a CMOS integrated circuit (IC) logic chip. Memory banks drive one line of a connected global data line pair to develop a difference signal on the pair. Simultaneously, a global signal monitor line discharges to develop a signal that mirrors the signal developing on one of the pair. When the global signal monitor line discharges sufficiently to indicate that the difference signal is large enough to sense, a global sense control sets a global data sense amplifier, the memory banks drive shuts off, and the global sense control initiates restoring global data line.

REFERENCES:
patent: 5229967 (1993-07-01), Nogle et al.
patent: 5959918 (1999-09-01), Arimoto
patent: 6295244 (2001-09-01), Kim et al.
patent: 2005/0146957 (2005-07-01), Lee et al.

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