DRAM with refresh control function

Details DRAM with refresh control function DRAM with refresh control function

2005-08-23

2005-08-23

Ho, Hoai (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000, C365S230030

Reexamination Certificate

active

06934211

ABSTRACT:
A dynamic random access memory (DRAM) has a refresh-control function under control by an internal refresh-control signal. The DRAM includes: a cell array having a plurality of DRAM cells divided into a plurality of blocks, the DRAM cells being driven through word lines for data transfer with bit lines; a decoder to select word lines and bit lines connected to the cell array; a sense amplifier to amplify data on the bit lines; and a refresh controller to limit refresh to the cell array so that at least one externally-accessed block cell among the blocks is refreshed.

REFERENCES:
patent: 5623451 (1997-04-01), Kawagoe
patent: 6058061 (2000-05-01), Ooishi
patent: 6349068 (2002-02-01), Takemae et al.
patent: 05-109268 (1993-04-01), None

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