DRAM with reduced power consumption

Details DRAM with reduced power consumption DRAM with reduced power consumption

2008-01-24

2009-06-30

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S207000, C365S189090

Reexamination Certificate

active

07554870

ABSTRACT:
In one embodiment, a dynamic random access memory (DRAM) is provided that includes: a plurality of rows of memory cells, each of the memory cell rows being arranged into columns, wherein each of the memory cell rows is crossed by a row of four word lines, and wherein each of the columns is crossed by a bit line; a plurality of sense amplifiers corresponding to the bit lines such that a single sense amplifier corresponds to every four bit lines; and a plurality of 4:1 multiplexers corresponding to the plurality of sense amplifiers, each 4:1 multiplexer coupling its corresponding sense amplifier to its corresponding four bit lines.

REFERENCES:
patent: 6677880 (2004-01-01), Yamamoto
patent: 6903953 (2005-06-01), Khanna
patent: 6967856 (2005-11-01), Park et al.
patent: 7006368 (2006-02-01), Arsovski et al.
patent: 2003/0063501 (2003-04-01), Covarel et al.
patent: 2004/0032759 (2004-02-01), Chow et al.
patent: 2006/0067134 (2006-03-01), Zhang et al.

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