DRAM with reduced electric power consumption

Details DRAM with reduced electric power consumption DRAM with reduced electric power consumption

1996-10-04

1999-02-02

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Data refresh

365236, G11C 700

Patent

active

058674381

ABSTRACT:
A DRAM (dynamic Random Access Memory) having a plurality of memory cells includes a data read/write circuit reading or writing data for the memory cells, a self-refresh circuit refreshing data stored in the memory cells, and a power supply unit for supplying electric power to the data read/write circuit and the self-refresh circuit, the electric power having a first voltage level in a normal operation mode and a second voltage level in a self-refresh mode, wherein the second voltage level is lower than the first voltage level.

REFERENCES:
patent: 4943960 (1990-07-01), Komatsu et al.
patent: 5132932 (1992-07-01), Tobita
patent: 5268865 (1993-12-01), Takasugi
patent: 5311483 (1994-05-01), Takasugi
patent: 5337282 (1994-08-01), Koike
patent: 5477491 (1995-12-01), Shirai
patent: 5566117 (1996-10-01), Okamura

Affiliated with

Also associated with

Rating

DRAM with reduced electric power consumption does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM with reduced electric power consumption, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM with reduced electric power consumption will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1123708