DRAM with memory cells having access transistor formed on solid

Details DRAM with memory cells having access transistor formed on solid DRAM with memory cells having access transistor formed on solid

1991-11-26

1994-09-13

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257347, H01L 2978, H01L 2300

Patent

active

053471512

ABSTRACT:
Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon layer and over a field oxide film. Part of the stacked capacitor extends over the bit line. The connection region of the bit line, the capacitor and the source/drain is formed above the element isolation and insulation film, so that the source/drain region of the access transistor can be reduced.

REFERENCES:
patent: 5138412 (1992-08-01), Hieda et al.
patent: 5196910 (1993-03-01), Moriuzki et al.
A. Moschwitzer, Halbleiterelektronik, 7th ed., Dr. A. Huthing Verlag Heidelberg, 1987, pp. 341-342.
Shin'Ichiro Kimura et al., "A Diagonal Active-Area Stacked Capacitor DRAM Cell with Storage Capacitor on Bit Line", IEEE Transactions on Electron Devices, vol. 37, Nr. 3, Mar. 1990, 737-743.

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