DRAM with interleaved folded bit lines

Details DRAM with interleaved folded bit lines DRAM with interleaved folded bit lines

1981-12-04

1984-10-09

Larkins, William D.

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

357 23, 357 41, 357 45, 365149, 365208, H01L 2704, G11C 1140

Patent

active

044765479

ABSTRACT:
The present invention discloses a memory cell layout of a dynamic RAM of a folded bit line type MOS FET wherein the bit line pairs are extended in parallel away from the sense amplifiers.
The present invention includes a particular bit line pair and at least one bit line of an adjacent bit line pairs positioned between the particular bit line pair and makes the capacitor regions corresponding to the mutually adjacent bit lines interleave and thereby improves the area efficiency of the capacitor region.

REFERENCES:
patent: 4044340 (1977-08-01), Itoh
patent: 4160275 (1979-07-01), Lee et al.
patent: 4216489 (1980-08-01), Clemens et al.
patent: 4355374 (1982-10-01), Sakai et al.
IEEE Transactions on Electron Devices, V. L. Rideout, vol. ED26, No. 6, Jun. 1979, pp. 846-847.
IBM Technical Disclosure Bulletin, K. L. Anderson, vol. 20, No. 11A, Apr. 1978, pp. 4295-4296.

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