DRAM with high bandwidth interface that uses packets and arbitra

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

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364DIG1, G06F 1200

Patent

active

057784191

ABSTRACT:
A memory chip for storage and retrieval of data transmitted as streams of data at sustained peak data transfer rates. The memory chip includes a memory device and an interface capable of achieving high bandwidth throughput. The memory device decodes, arbitrates between, and executes memory access commands, and generates memory access responses. The interface includes a data path, and a number of memory controllers. The interface receives and transmits input and output data streams, and the memory controllers control the flow of the input and output data streams within the memory chip. A packet buffer is coupled between the data path and the memory device. The packet buffer provides for temporary storage of memory access commands, response information, and forwarding data.

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patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5606717 (1997-02-01), Parmwald et al.

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