DRAM variable row select

Details DRAM variable row select DRAM variable row select

1993-02-04

1994-07-19

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36523006, 365222, 365227, 365228, 36518905, G11C 800

Patent

active

053316010

ABSTRACT:
A memory device circuit that alters the input refresh addresses to access fewer memory cells to save power, or to address more memory cells to decrease the refresh time. The circuit contains a simple transistor configuration that blocks certain address bits, then substitutes active bits in their place to the address decoder. The circuit also includes a controller that is responsive to the memory device entering the refresh mode. When the device is used in refresh mode, the address bits may be passed unblocked to the address decoder for full user control.

REFERENCES:
patent: 4989183 (1991-01-01), Kumanoya et al.

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