DRAM trench cell

Details DRAM trench cell DRAM trench cell

1999-08-31

2002-04-30

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000, C257S907000, C257S908000

Reexamination Certificate

active

06380575

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit manufacturing techniques and more particularly to an improved method and structure to improve the conductive strap electrical connection between a storage device and a pass gate device.
2. Description of the Related Art
Integrated circuit devices such as dynamic random access memories (DRAM) are being continually reduced in size to decrease manufacturing costs and to increase speed. However, as the devices are scaled (e.g., reduced in size), the manufacturing tolerances including size control and positional overlay must be reduced. Therefore, as integrated circuits are scaled, defects resulting from improperly shaped or positioned items often result in circuits which do not perform as intended, reducing manufacturing yield.
In order to avoid such defects, open-bitline or hierarchical architectures are used to help chip area scaling. An open bitline cell may require a bitline that has a direction off-orthogonal to the wordline direction. A discontinuity of the array is required to change the direction of an off-orthogonal bitline. Such a discontinuity of the array will inflict an undesirable area penalty in the chip.
Other similar scaling processes may place the buried strap in direct proximity to the array device channel. If the buried strap is in direct proximity to the device channel, the buried strap outdiffusion region will interact with the array device source drain diffusion, and impact device performance such as off-current and threshold voltage.
Therefore, there is a need to reduce the size of integrated circuit devices and allow more devices to be placed on a chip, without comprising the functionality of the devices.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit chip that includes storage devices, isolation regions adjacent the storage devices and surface straps connected to the storage devices, wherein the isolation regions have a border coincident with a border of the surface straps.
The isolation regions have a step-shape for accommodating the surface straps and have a comer which matches a comer of the surface straps. Thus, the isolation regions are free from interfering with a connection between the surface straps and the storage devices.
The storage devices and the isolation regions are formed on a substrate and the storage devices and the isolation regions define active areas in the substrate. The integrated circuit chip includes bitline contacts in the active areas. The integrated circuit chip includes serpentine gate conductors positioned between the surface straps and the storage devices. The storage devices can be deep trench storage devices and the surface strap connects the deep trench storage devices to transistors.
An inventive method for forming an integrated circuit chip includes forming storage devices, forming isolation regions adjacent the storage devices and forming surface straps connected to the storage devices, wherein the isolation regions are formed to have a border coincident with a border of the surface straps. The isolation regions are formed to have a step-shape for accommodating the surface straps and to have a comer which matches a comer of the surface straps. The isolation regions are formed to be free from interfering with a connection between the surface straps and the storage devices.
The invention increases the overlap area between the surface strap and the deep trench storage device which provides greater reliability of the connection, reduces the number of defects and increases manufacturing yields.


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