DRAM that stores multiple bits per storage cell

Details DRAM that stores multiple bits per storage cell DRAM that stores multiple bits per storage cell

1999-12-31

2000-10-31

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Including signal comparison

365 45, 365210, G11C 700

Patent

active

061412619

ABSTRACT:
A memory constructed from a plurality of data storage words. Each data storage word includes a plurality of data storage cells and a plurality of reference storage cells, each data storage cell and each reference storage cell having at least 4 states. The memory has a plurality of reference lines, one such reference line corresponding to each reference storage cell. The corresponding reference storage cell is connected to that reference line by a gate included in that storage cell. Each reference cell assumes one of the states in response to a signal on the corresponding reference line and a write signal, the state being determined by the signal on the corresponding reference line. The memory also includes a plurality of data lines, one such data line corresponding to each data storage cell, the corresponding data storage cell being connected to that data line by a gate in that storage cell. Each data cell assumes one of the states in response to a signal on the corresponding data line and a write signal, the state being determined by the signal on the corresponding data line. A plurality of reference encoding circuits determines the state stored by each reference cell, there being one such reference encoding circuit corresponding to each reference line. The preferred data storage cell includes first, second, and third gates, and a capacitor for storing a charge that determines the current sinked by the third gate. The preferred data encoding circuit utilizes a current-mode digital to analog converter. Data is read from the memory by a plurality of data decoding circuits that generate a digital value representing the current flowing in the corresponding data line by comparing that current to currents flowing in each of the reference lines.

REFERENCES:
patent: 5847991 (1998-12-01), Tong et al.

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