DRAM supporting different burst-length accesses without...

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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Details

C711S105000, C711S167000, C710S035000, C365S239000

Reexamination Certificate

active

06957308

ABSTRACT:
A memory device may be implemented to respond to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for the memory device. For example, a memory device may include a memory array and a mode register configured to store a value indicating a current burst length. The memory array may be configured to perform a first burst access having a first burst length in response to receiving a first command encoding and to perform a second burst access having a second burst length, which does not equal the current burst length, in response to receiving a second command encoding. A memory controller may be implemented to generate to and one or more command encodings that specify different burst lengths than the burst length indicated by the current burst length setting for a targeted memory device.

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patent: 6226724 (2001-05-01), Biggs
patent: 6393500 (2002-05-01), Thekkath
patent: 6549991 (2003-04-01), Huang et al.
patent: 6564287 (2003-05-01), Lee
patent: 6615325 (2003-09-01), Mailloux et al.
patent: 2001/0010096 (2001-07-01), Horton, Jr., et al.
patent: 2001/0039602 (2001-11-01), Kanda et al.
patent: 2002/0031020 (2002-03-01), Ozawa et al.
patent: 2003/0204674 (2003-10-01), Ryan et al.
International search report application No. PCT/US03/21286 mailed Dec. 9, 2003.

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