DRAM storage node with insulating sidewalls

Details DRAM storage node with insulating sidewalls DRAM storage node with insulating sidewalls

2000-01-12

2002-11-19

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S300000, C438S238000, C438S239000, C438S386000

Reexamination Certificate

active

06483140

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a dynamic random-access memory of capacitor-over-bit-line construction and a method of manufacturing the same.
2. Description of the Background Art
The construction of a conventional dynamic random-access memory (DRAM) of capacitor-over-bit-line construction (COB) and a method of manufacturing the same will be described with reference to
FIGS. 9 and 10
.
FIG. 9
is a plan view of a workpiece in one stage of a method of manufacturing the DRAM of capacitor-over-bit-line construction, and
FIG. 10
is a sectional view taken on line X—X in FIG.
9
.
The conventional DRAM has a silicon substrate
1
. An isolating silicon oxide film
2
for isolating a plurality of active regions is formed on the silicon substrate
1
. Channel regions covered with a gate silicon oxide film
3
and transfer gates (TGs)
4
, and source/drain regions
5
adjacent to the channel regions are formed in the active regions.
A lower insulating film
6
of silicon nitride is formed over the silicon substrate
1
and the TGs
4
. A first upper insulating film
7
is formed over the lower insulating film
6
. Contact holes
8
opening into the source/drain regions
5
are formed in the first upper insulating film
7
by a known self-alignment process. Bit lines (BLs)
9
are formed on the first upper insulating film
7
so as to be connected through the contact holes
8
to the source/drain regions
5
.
A second upper insulating film
10
is formed over the first upper insulating film
7
and the BLs
9
. Storage node contacts (SCs)
11
are formed through the first upper insulating film
7
and the second upper insulating film
10
so as to open to the source/drain regions
5
. As shown in
FIG. 9
, the SCs
11
are arranged between the TGs
4
and the BLs
9
.
Capacitors, not shown, are formed on the second upper insulating film
10
so as to be electrically connected through the SCs
11
to the source/drain regions
5
. Side walls
13
are formed on at least lower end portions of the SCs
11
to prevent short circuit between the capacitors and the TGs
4
or the BLs
9
.
When manufacturing the conventional DRAM, the contact holes
8
for the BLs
9
are formed by a self-alignment method. The self-alignment method etches the first upper insulating film
7
(silicon oxide film) by an etching process using the lower insulating film
6
(silicon nitride film) as a stopper film on process conditions for etching the first upper insulating film
7
at a high selectivity relative to the lower insulating film
6
. Subsequently, the lower insulating film
6
is removed by anisotropic etching to form the contact holes
8
opening to the source/drain regions
5
. Thus, the contact holes
8
can be formed in self-alignment with the source/drain regions
5
so as to open to the source/drain regions
5
regardless of the accuracy of a photolithography process.
When manufacturing the conventional DRAM, the SCs
11
are formed through the second upper insulating film
10
, the first upper insulating film
7
and the lower insulating film
6
(hereinafter referred to inclusively as “layer insulating films
6
,
7
and
10
”) by anisotropic etching. The side walls
13
are formed by depositing an insulating film over the surface of the silicon substrate
1
and in the SCs
11
, and etching portions of the insulating film deposited in the SCs
11
by anisotropic etching so that the source/drain regions
5
formed in the silicon substrate
1
are exposed.
The SCs
11
, similarly to the contact holes
8
for the BLs
9
, are through holes penetrating the silicon oxide films (the first upper insulating layer
7
and the second upper insulating layer
10
) and the silicon nitride film (the lower insulating film
6
). Therefore, the SCs
11
can be formed by a self-alignment method. However, in the DRAM of COB construction, the aspect ratio of the SCs
11
is large as compared with that of the contact holes
8
.
The greater the aspect ratio of holes to be formed, the more difficult is the control of selectivity. If an etching process for forming the SCs
11
is performed under the conditions identical to those employed for opening the contact halls
8
, i.e. the conditions that enable the removal of a silicon oxide film at a high selectivity, a state may occurs in which a desired selectivity can be achieved for regions corresponding to flat portions of the silicon nitride film (lower insulating film
6
), but a desired etch selectively cannot be achieved for regions corresponding to corners of the silicon nitride film.
To make a self-alignment effect effective when forming the SCs
11
, even if the corners of the lower insulating film
6
is exposed to etching gas, the silicon oxide film must be etched at a high selectivity. Thus, regarding with the formation of the SCs
11
, because of the large aspect ratio thereof, it is difficult to make a self-alignment effect effective even if an etching process capable of selectively etching the silicon oxide film and the silicon nitride film is employed. Accordingly, the conventional manufacturing method forms the SCs
11
by anisotropic etching capable of removing both the silicon oxide film and the silicon nitride film to simplify the manufacturing processes.
Conditions for the anisotropic etching to form the SCs
11
must be determined so as to be suitable for etching portions of the layer insulating films
6
,
7
and
10
having a maximum thickness to avoid forming faulty openings. Since the respective thicknesses of the layer insulating films
6
,
7
and
10
are irregular, portions of the silicon substrate
1
exposed to the SCs
11
and corresponding to thin portions of the layer insulating films
6
,
7
and
10
may be etched excessively in some cases as shown in FIG.
10
. Similarly, in some cases, portions of the silicon substrate
1
exposed in the SCs
11
may be removed excessively by etching for forming the side walls
13
. Such damage to the silicon substrate
1
will increase leakage current at PN junctions, which affects adversely to the refreshing characteristic, i.e., basic characteristic, of the DRAM.
The conventional method forms the side walls
13
(silicon nitride films) after forming the SCs
11
so as to open to the source/drain regions
5
. Therefore, lower end portions of the side walls
13
are in contact with damaged portions of the source/drain regions
5
damaged when the SCs
11
are formed. When the silicon nitride films are in direct contact with the damaged portions of the source/drain regions
5
, electrons are liable to be trapped by the silicon nitride films when the DRAM operates. Therefore, in the conventional DRAM, the damage done to the substrate during the formation of the SCs
11
may affects adversely to the characteristics of the transistors.
FIG. 11
is a sectional view of a structure formed when a photolithography process for forming the SCs
11
is inaccurate. In the structure shown in
FIG. 11
, a pattern is formed by photolithography process so that the SCs
11
are formed at positions corresponding to the corners of the lower insulating film
6
.
When forming the DRAM by the conventional method, it sometimes occurs that the isolation silicon oxide film
2
is etched by a depth greater than that of the bottom surfaces of the source/drain regions
5
as shown in
FIG. 11
when the SCs
11
are formed at the foregoing positions. In the SCs
11
are formed storage node electrodes of doped polysilicon so as to be connected to the capacitors. If the isolation silicon oxide film
2
is etched excessively, the storage node electrodes of doped polysilicon are in contact with the silicon substrate
1
at a depth greater than that of the source/drain regions
5
. Consequently, the impurity diffuses from the storage node electrodes of doped polysilicon into the silicon substrate
1
and cells cannot satisfactorily be isolated by the isolation silicon oxide film
2
.
SUMMARY

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