DRAM stack capacitor with ladder storage node

Details DRAM stack capacitor with ladder storage node DRAM stack capacitor with ladder storage node

1995-06-23

1997-05-20

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257534, H01L 27108

Patent

active

056314809

ABSTRACT:
A method, and resultant structure, is described for fabricating a DRAM (Dynamic Random Access Memory) cell having a stack capacitor with a ladder storage node, connected to a MOS (Metal Oxide Semiconductor) transistor with source and drain regions, to form a DRAM cell. A bottom electrode is connected to and extends up from the source region of the transistor, and has a top surface with a central cavity, and side surfaces extending down from the top surface in a step-like manner. These step-like sides are formed by a repeated two-step process of removing a portion of the vertical walls of a photoresist mask and removing a portion of the top surface of a layer of polysilicon from which the bottom electrode is formed. There is a capacitor dielectric over the bottom electrode. A top electrode is formed over the capacitor dielectric.

REFERENCES:
patent: 5110752 (1992-05-01), Lu
patent: 5162881 (1992-11-01), Ohya
patent: 5183772 (1993-02-01), Jin et al.
patent: 5245206 (1993-09-01), Chu et al.
patent: 5326998 (1994-07-01), Jun

Affiliated with

Also associated with

Rating

DRAM stack capacitor with ladder storage node does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM stack capacitor with ladder storage node, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM stack capacitor with ladder storage node will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1725720