Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-06-19
2001-09-18
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S206000, C257S303000, C257S306000
Reexamination Certificate
active
06291846
ABSTRACT:
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a dynamic random access memory (DRAM) semiconductor device and its manufacture.
In this specification, a DRAM semiconductor device means a semiconductor device having a DRAM portion, and also includes those having other functional elements.
b) Description of the Related Art
One DRAM cell is generally made of one memory capacitor and one transistor. This transistor is generally an insulating gate (IG) field effect transistor (FET), and typically a metal-oxide-semiconductor (MOS) FET, which is constituted of a pair of source/drain regions, a channel coupling the source/drain regions, and an insulated gate electrode disposed over the channel for controlling the conductivity of the channel.
A memory capacitor is connected to one of the pair of source/drain regions (which is called a source for convenience sake), and a bit line is connected to the other (which is called a drain for convenience sake). A word line is connected to the insulated gate electrode.
For the implementation of a number of memory cells in a limited rectangular area and for the effective read/write of information, it is preferable to dispose bit and word lines orthogonally. Each memory cell is connected to each cross point between bit and word lines.
If one drain region is shared by two transistors and connected to a bit line, an area occupied per one transistor can be reduced. In this case, integrated or merged two transistors are formed in one active region, and the bit line is connected to the central drain region. In order to connect memory capacitors to two sources at opposite end portions of the active region, it is preferable to dispose the active region obliquely relative to the bit lines. Then, word lines become also oblique relative to active regions.
One of the present inventors, Ema, has proposed a DRAM semiconductor device in which the layout of an active region and word lines of each memory cell is devised to stabilize the threshold values of transistors even under misalignment of patterning (Japanese Patent Laid-open Publication HEI-2-192162 and U.S. Pat. No. 5,014.013 issued on May 7, 1991, which are incorporated herein by reference).
FIG. 5
shows the layout of memory cells proposed by Ema. A plurality of bit lines BL extend straight and in parallel in the horizontal direction in FIG.
5
. Bit lines disposed straight can minimize their resistance values. Each active region AR is disposed obliquely (about 30 degrees) relative to bit lines BL.
In an area where the active region AR crosses the bit line BL, a contact portion BL′ of the bit line is formed which is wider than the other portion of the bit line. A bit line contact hole BH is formed through an interlayer insulating film disposed between the active region AR and bit line BL. A capacitor contact hole SH is disposed generally at the center of an area surrounded by two adjacent bit lines BL and two adjacent word lines WL. Namely, the distance from the capacitor hole to nearest bit/word lines is maximized.
A storage electrode SE of the capacitor is disposed around the capacitor contact hole SE in an area between upper and lower bit lines BL, the electrode covering the adjacent word line.
In the area between the bit line contact hole BH and capacitor contact hole SH, the active region AR extends straight at a constant width. The active region AR includes a region AR′ to reserve an area under the capacitor contact hole, this region AR′ having a shape symmetrically folded relative to a virtual vertical line passing through the center of the capacitor contact hole SH.
A word line WL extends as a whole in a vertical direction of FIG.
5
. However, this word line is curved around the center of the contact hole of the bit line BL In an area crossing the bit line, connected to the corresponding active region AR. The word line WL can therefore be disposed generally at a right angle relative to the active region AR. With this layout, even if there is any position alignment error between the word line WL and active region AR, the threshold value of each transistor can be maintained constant.
SUMMARY OF THE INVENTION
An object of the invention is to improve the above-described proposal made by one of the present inventors.
Another object of the invention is to provide a DRAM semiconductor device having stable and excellent characteristics.
According to one aspect of the present invention, there is provided a DRAM semiconductor device comprising: a semiconductor substrate; a field insulating film formed on the semiconductor substrate; a plurality of active regions each surrounded by the field insulating film and formed in the semiconductor substrate; a gate electrode traversing each of the plurality of active regions; a pair of source/drain regions, formed in each of the plurality of active regions on both sides of the gate electrode; a plurality of bit lines disposed along one direction each connected to one of the pair of source/drain regions; a plurality of word lines disposed along a direction perpendicular to the bit lines, each of the plurality of word lines being connected to the gate electrode; and a plurality of capacitor elements disposed over the gate electrode each connected to the other of the pair of source/drain regions, wherein each of the plurality of active regions includes an oblique area formed obliquely relative to the bit and word lines and a parallel area formed in parallel to the bit line and having a width greater than the width of the oblique area, and the word lines have a bent portion intersecting at substantially a right angle with the oblique area of the active region.
According to another aspect of the invention, there is provided a DRAM semiconductor device comprising: a semiconductor substrate; a plurality of parallel bit lines disposed over the semiconductor substrate and linearly extending along one direction; a plurality of active regions formed on the surface of the semiconductor substrate, each of the active regions including a linear stripe area whose central area intersects with the bit line at a first angle and opposite end areas continuous with the opposite ends of the stripe area in a longitudinal direction thereof each having a width greater than a width of the stripe area; a field insulating film formed on the semiconductor substrate and having openings which define the plurality of active regions; a bird's beak insulating film formed on the surface of the active region of the semiconductor substrate along an inner circumference of the opening of the field insulating film and defining an intrinsic active region at an inner area of the bird's beak insulating film and defining a quasi-active region under the bird's beak insulating film; a plurality of word lines formed over the semiconductor substrate and intersecting as a whole at substantially a right angle with the bit lines, two of the word lines being associated with each active region, and each of the plurality of word lines having a bent portion intersecting at substantially a right angle with the stripe area over an associated one of the active regions and having substantially no overlap with a non-associated one of the active regions; one drain and a pair of sources formed in each of the intrinsic active regions, the one drain being formed between associated two of the word lines, and the pair of sources being formed outside of the associated two of the word lines; and a storage capacitor connected to each of the sources.
According to yet another aspect of the present invention, there is provided a method of manufacturing a DRAM semiconductor device comprising the steps of: forming a field insulating film on a semiconductor surface, the field insulating film surrounding active regions, each including an oblique area oblique to one reference direction and a parallel area parallel to the one reference direction having a width greater than a width of the oblique area; f
Ema Taiji
Masuda Koichi
Saitoh Satoru
Shinmoto Tamon
Armstrong Westerman Hattori McLeland & Naughton LLP
Crane Sara
Fujitsu Limited
Tran Thien F.
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