DRAM refreshment

Details DRAM refreshment DRAM refreshment

2007-01-09

2007-01-09

Phung, Ahn (Department: 2824)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S205000, C365S207000

Reexamination Certificate

active

10627955

ABSTRACT:
A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.

REFERENCES:
patent: 5537359 (1996-07-01), Toda
patent: 5590080 (1996-12-01), Hasagawa et al.
patent: 5822264 (1998-10-01), Tomishima et al.
patent: 5822266 (1998-10-01), Kikinis
patent: 5995433 (1999-11-01), Liao
patent: 6075736 (2000-06-01), Kim et al.
patent: 6097658 (2000-08-01), Satoh et al.
patent: 6515930 (2003-02-01), Jacquet et al.
patent: 6801467 (2004-10-01), Ferrant et al.
French Search Report from French Patent Application No. 00/17294, filed Dec. 29, 2000.

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