DRAM refresh control circuit

Details DRAM refresh control circuit DRAM refresh control circuit

1995-01-03

1996-05-07

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365233, G11C 700

Patent

active

055153313

ABSTRACT:
A control circuit for refreshing a dynamic random access memory (DRAM) having a plurality of memory cells arranged in rows and columns. The inventive refresh control circuit includes a first circuit for detecting whether a first refresh mode exists in response to row and column address signals applied thereto and for generating a first output signal based on the result of the detection; a second circuit for detecting whether a second refresh mode exists in response to row and column address signals applied thereto and for generating a second output signal based on the result of the detection; a third circuit for detecting whether a reset condition exists in response to row and column address signals applied thereto and for generating a reset signal based on the result of the detection; and a counter circuit, coupled to the first, second, and third detecting circuits, for generating a count value representing a refresh address in response to the first and second output signals and the reset signal.

REFERENCES:
patent: 4158883 (1979-06-01), Kadano et al.
patent: 4207618 (1980-06-01), White, Jr. et al.
patent: 4296480 (1981-10-01), Eatson, Jr. et al.
patent: 4716551 (1987-12-01), Inagaki
patent: 5343430 (1994-08-01), Furuyama
patent: 5400290 (1995-03-01), Suma

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