DRAM power management in a memory controller

Details DRAM power management in a memory controller DRAM power management in a memory controller

2007-07-10

2010-06-15

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C365S194000, C365S226000, C365S227000, C710S309000, C713S322000

Reexamination Certificate

active

07739461

ABSTRACT:
A memory controller uses a power- and performance-aware scheduler which reorders memory commands based on power priorities. Selected memory ranks of the memory device are then powered down based on rank localities of the reordered commands. The highest power priority may be given to memory commands having the same rank as the last command sent to the memory device. Any memory commands having the same power priority can be further sorted based on one or more performance criteria such as an expected latency of the memory commands and an expected ratio of read and write memory commands. To optimize the power-down function, the power-down command is only sent when the selected memory rank is currently idle, the selected memory rank is not already powered down, none of the reordered memory commands correspond to the selected rank, and a currently pending memory command cannot be issued in the current clock cycle.

REFERENCES:
patent: 5835435 (1998-11-01), Bogin et al.
patent: 7334144 (2008-02-01), Schlumberger
patent: 2005/0027952 (2005-02-01), Mayo et al.
patent: 2006/0064532 (2006-03-01), Hur
patent: 2006/0112240 (2006-05-01), Walker et al.

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