DRAM power management

Details DRAM power management DRAM power management

2005-08-30

2005-08-30

Padmanabhan, Mano (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S154000, C711S156000, C713S320000, C713S321000, C713S322000, C713S323000, C713S330000, C713S340000, C713S400000, C713S401000, C713S500000, C713S501000

Reexamination Certificate

active

06938119

ABSTRACT:
A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system. Alternatively, if the memory access rate has been exceeded, then the access is delayed until the current time interval has expired and a subsequent time interval is started as the current time interval and the access is applied to the memory system.

REFERENCES:
patent: 3736569 (1973-05-01), Bouricius et al.
patent: 5083266 (1992-01-01), Watanabe
patent: 6021076 (2000-02-01), Woo et al.
patent: 6151681 (2000-11-01), Roden et al.
patent: 0 777 182 (1997-06-01), None
patent: WO92/10032 (1992-06-01), None
PCT International Search Report (4 pages).

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