Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1994-11-28
2000-09-26
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714804, H03M 1300
Patent
active
061254665
ABSTRACT:
A scheme for protecting memory stored in a DRAM using a combination of horizontal and vertical parity data to detect and correct errors in a protected space of memory in which code is stored. The DRAM memory of this scheme is architected with the code stored in horizontally contiguous bytes and the vertical parity, generated when the code is compiled, also stored in horizontally contiguous bytes, but in a row of DRAM memory separate from those in which the code is stored.
REFERENCES:
patent: 3183483 (1965-05-01), Lisowski
patent: 3831144 (1974-08-01), En
patent: 3887901 (1975-06-01), Moore, III
patent: 4183463 (1980-01-01), Kemmetmueller
patent: 4231089 (1980-10-01), Lewine et al.
patent: 4277844 (1981-07-01), Hancock et al.
patent: 4371963 (1983-02-01), Edwards, Jr. et al.
patent: 4453251 (1984-06-01), Osman
patent: 4464747 (1984-08-01), Groudan et al.
patent: 4688219 (1987-08-01), Takemae
patent: 4747080 (1988-05-01), Yamada
patent: 5090014 (1992-02-01), Polich et al.
patent: 5107505 (1992-04-01), Lelandais et al.
Campbell Bryan T.
Close Ciaran B.
Gahan Richard A.
Beausoliel, Jr. Robert W.
Cabletron Systems Inc.
Elisca P.
LandOfFree
DRAM parity protection scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DRAM parity protection scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM parity protection scheme will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2109398