DRAM parity protection scheme

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

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714804, H03M 1300

Patent

active

061254665

ABSTRACT:
A scheme for protecting memory stored in a DRAM using a combination of horizontal and vertical parity data to detect and correct errors in a protected space of memory in which code is stored. The DRAM memory of this scheme is architected with the code stored in horizontally contiguous bytes and the vertical parity, generated when the code is compiled, also stored in horizontally contiguous bytes, but in a row of DRAM memory separate from those in which the code is stored.

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