Static information storage and retrieval – Read/write circuit – Parallel read/write
Patent
1994-04-11
1997-04-29
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Parallel read/write
36518901, 3652385, G11C 700
Patent
active
056256019
ABSTRACT:
A method of transferring data into or out of plural memory cells of a dynamic random access memory (DRAM) comprised of precharging bitlines of the DRAM for a predetermined interval, addressing a first group of wordlines for a first period of time, after the first period of time, addressing a second group of wordlines for a second period of time, the first and second periods of time being contained within the predetermined interval, addressing and sensing a first group of memory cells from the first group of wordlines for an interval within the first period of time, addressing a second group of memory cells from the second group of wordlines within the second period of time, and transferring sensed bits from the first group of memory cells to the second group of memory cells while the second group of memory cells is being addressed.
REFERENCES:
patent: 4639894 (1987-01-01), Ishii
patent: 5245585 (1993-09-01), Voss et al.
patent: 5381368 (1995-01-01), Morgan et al.
"Serial-Access Page-Mode Memory," by R.E. Scheuerlein, IBM Technical Disclosure Bulletin, vol. 27, No. 7B, Dec. 1984, pp. 4426-4428.
Gillingham Peter B.
Torrance Randy
Dinh Son
Mosaid Technologies Incorporated
Nelms David C.
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