DRAM output circuitry supporting sequential data capture to...

Details DRAM output circuitry supporting sequential data capture to... DRAM output circuitry supporting sequential data capture to...

2003-02-11

2004-06-22

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S207000, C365S208000

Reexamination Certificate

active

06754120

ABSTRACT:

BACKGROUND
FIG. 1
(prior art) depicts memory system
100
that includes a memory core
105
connected to a serial input/output (I/O) pipeline
110
. Core
105
includes an array
115
of memory cells
120
, each of which connects to one of wordlines WL<
0
,
1
> and one of bitlines BL<
0
:
15
>. For example, the upper-most memory cell
120
connects to a word line WL<
1
> and a bitline BL<
0
>. The bitlines convey data signals from cells
120
to corresponding input nodes of a collection of bitline sense amplifiers
130
, also called “sense amps.” Sense amps
130
amplify the data signals and provide the resulting data to a read/write data line RWD within I/O pipeline
110
via complementary input/output lines I/O and I/Ob. The read/write data lines RWD<
0
:
3
> convey data both to and from array
115
. Other memory systems employ separate read and write data lines. The following description is limited to read operations, for brevity, so read/write data lines RWD<
0
:
3
> are referred to as read data lines.
Each bitline sense amp
130
includes a pair of complementary output nodes that connect to pipeline
110
via a respective column-select switch
135
. Column-select switches
135
divide memory array
115
into a number of columns, two in the simple example of FIG.
1
. When data is being read from memory array
115
, data signals presented on the read/write data lines RWD are conveyed to the input nodes of a collection of read sense amps
140
. Read sense amps
140
convey the resulting amplified signals to an output register or output buffer
145
. Once the data from the selected column is loaded into register
145
, the contents of register
145
are shifted out via a pair of complementary data output pins DQ and DQb. Other memory systems include just one data output pin.
Memory cells
120
connect to bits
150
within output buffer
145
via routing resources that vary from one memory cell to the next. The time required for individual cells
120
to present data to output register
145
in response to a read request therefore likewise varies from one cell to the next. Due to these timing variations, output buffer
145
must await the slowest memory cell before shifting out data. In effect, the memory access time T
AC
(sometimes called the “data access time” t
DAC
or T
CAC
) is limited by the speed performance of the slowest memory cell
120
within memory core
115
.
Newer memory interface technologies, such as the high-speed interface from Rambus used in conjunction with Rambus Direct RDRAM memories, are capable of extracting data from memory array
115
faster than memory array
115
is able to provide data to output buffer
145
. This bottleneck is expected to become more problematic in succeeding generations of high-performance memories.
SUMMARY
The present invention improves the speed at which dynamic memory systems produce data extracted from core memory. Memory systems in accordance with some embodiments are designed to emphasize differences between memory-cell access times. As a consequence of these access-time variations, data read from different memory cells arrives at some modified output circuitry. The output circuitry sequentially offloads the data in the order of arrival. Data access times are reduced because the output circuitry can begin shifting the first data to arrive before the slower data is ready for capture.
Differences between data access times for cells in a given memory array may be emphasized using differently sized sense amplifiers, routing, or both. One embodiment, for example, includes differently sized sense amplifiers to provide differently timed data-access paths.
This summary does not limit the invention, which is instead defined by the issued claims.


REFERENCES:
patent: 4837465 (1989-06-01), Rubinstein
patent: 5546346 (1996-08-01), Agata et al.
patent: 5748561 (1998-05-01), Hotta
patent: 5751657 (1998-05-01), Hotta
patent: 5936885 (1999-08-01), Morita et al.
“Design Optimization Techniques for Double Data Rate SDRAM Modules.” Fairchild Semiconductor, Jul. 2000. 6 pages.

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