DRAM MOS field effect transistors with thresholds determined...

Details DRAM MOS field effect transistors with thresholds determined... DRAM MOS field effect transistors with thresholds determined...

2000-10-06

2003-06-03

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C257S407000, C257S412000, C257S413000, C438S217000, C438S276000, C438S289000, C438S291000

Reexamination Certificate

active

06573575

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device such as DRAM (dynamic random access memory) having transistors having different threshold voltages, and a method for fabricating the same.
The DRAM comprises a memory cell array composed of a number of memory cells for storing information, and a peripheral circuit including a decoding circuit for selecting a memory cell, the memory cells and the peripheral circuit being formed on the same semiconductor substrate. Recently, a memory-logic mixed construction has been adopted in which the DRAM and a logic circuit developed by a user are formed on the same semiconductor substrate. In this specification, it should be understood that the peripheral circuit includes the logic circuit.
A memory cell includes a capacitor accumulating a signal charge for storing information, and a transistor functioning as a switching device for accumulating the signal charge into the capacitor and for reading out the signal charge accumulated in the capacitor. Incidentally, the transistor is ordinarily constituted of a FET (field effect transistor) having a MOS (metal oxide semiconductor) structure or a MIS (metal insulator semiconductor), because these transistors are convenient for realizing a high integration density. In addition, the peripheral circuit is constituted of FETs having the same structure as that of the transistor used in the memory cell, in order to make a fabricating processing in common with that for the memory cell. In the following, explanation will be made under the assumption that an n-channel MOS FET is used as transistors for the memory cells and transistors for the peripheral circuit.
When the n-channel MOS FET is used as transistors used in the DRAM, a recent MOSFET has a gate electrode (word line) formed of an n
+
polysilicon film or alternatively a multilayer film composed of a metal silicide and the n
+
polysilicon film (polycide film). This is because the work function of the n
+
silicon (Si) of the gate electrode is lower than the work function of a p-type silicon in a channel region by about 1V, so that it is possible to easily set the threshold of the FET at a low value.
On the other hand, it is known that, in the MOS FET, even when a gate voltage lower than the threshold voltage is applied, a drain current flows slightly. Here, the drain current flowing when the gate voltage is 0V, is called a subthreshold leak current If there is the subthreshold leak current in the FET used in the DRAM memory cell, the signal charge accumulated in the memory cell capacitor is discharged so that it becomes impossible to hold the signal charge. Therefore, the FET used in the DRAM memory cell is required to have as a small subthreshold leak current as possible.
In order to reduce the subthreshold leak current, it is sufficient if the threshold is set to be high. In the FET used in the DRAM memory cell, therefore, the threshold is set to be relatively high (on the order of 1.2V) in order to simultaneously prevent a malfunction caused by noises or others.
In the FET used in the peripheral circuit of the DRAM, on the other hand, the threshold is set to be relatively low (on the order of 0.4 to 0.6V) because reduction of an on-resistance to realize a high speed operation and reduction of a power consumption, are in preference to the reduction of the subthreshold leak current.
In the prior art DRAM, the threshold voltage was changed by making the impurity concentration of the channel region in the FET used in the peripheral circuit, different from the impurity concentration of the channel region in the FET of the memory cell. Specifically, the impurity concentration of the channel region in the FET of the memory cell is set to be five to ten times the impurity concentration of the channel region in the FET used in the peripheral circuit.
Referring to
FIG. 4
, there is shown a partial diagrammatic section view of the DRAM for illustrating one example of the prior art semiconductor device.
As shown in
FIG. 4
, the prior art DRAM includes a memory cell FET and a peripheral circuit FET which are formed on a p-type semiconductor substrate
1
and which are isolated from each other by a field oxide film
2
formed of an insulating film such as silicon dioxide (SiO
2
), in a shallowly embedded structure at a principal surface of the substrate.
As mentioned above, the memory cell is composed of an FET and a capacitor. Each of the memory cell FET and the peripheral circuit FET includes a drain region
3
and a source region
4
constituted of an n
+
diffused layer formed at the principal surface of the substrate, a channel region
5
or
15
formed between the drain region
3
and the source region
4
, a gate insulator film
6
formed on the principal surface of the substrate, directly above the channel region
5
or
15
, and constituted of an insulating film such as silicon dioxide (SiO
2
), and agate electrode formed of a n
+
polysilicon film
8
and a metal silicide film
9
stacked on the gate insulator film
6
.
The capacitor includes a capacitor lower electrode
11
connected to the drain
3
of the memory cell FET and becoming as one electrode of a pair of electrodes of a capacitor for holding information, a capacitor upper electrode
12
becoming as the other electrode of the capacitor, and a capacitor dielectric film
13
sandwiched between the capacitor lower electrode
11
and the capacitor upper electrode
12
.
Incidentally, each of he capacitor lower electrode
11
and the capacitor upper electrode
12
is formed of an n
+
polysilicon, and the capacitor dielectric film
13
is formed of a silicon nitride film (Si
3
N
4
). The memory cell FET and the peripheral circuit FET have the same structure, but the prior art DRAM was so formed that the impurity concentration of the channel region
15
in the peripheral circuit FET is lower than the impurity concentration of the channel region
5
in the memory cell FET. (Difference in impurity concentration is indicated in
FIG. 4
by difference in thickness of the dotted line in the channel region.)
Now, the method for fabricating the prior art DRAM shown in
FIG. 4
will be described with reference to
FIGS. 5A
to
5
F, which are diagrammatic sectional views of the DRAM for illustrating various steps of the semiconductor device fabricating process.
First, a silicon nitride film is formed on a principal surface of a p-type semiconductor substrate
1
, and is patterned to have a predetermined shape. The substrate exposed in an opening of the patterned silicon nitride film is selectively oxidized to form a field oxide film
2
having the thickness on the order of 300 nm, which constitutes an inactive region for a device isolation, as shown in FIG.
5
A.
Succeedingly, a pad oxide film
20
having the thickness on the order of 20 nm is formed on the whole of the principal surface of the substrate by means of a thermal oxidation. In order to form the channel regions
5
and
15
of the FETs, boron (B) is ion-implanted through the pad oxide film
20
with an energy of 30 KeV and a dose of 1 to 2×10
12
atoms/cm
2
(FIG.
5
B).
Then, a photoresist
21
is formed on the substrate to cover a region in which the peripheral circuit. FET is formed, and boron (B) is further ion-implanted into a region in which the memory cell FET is formed, with an energy of 30 KeV and a dose of 7 to 8×10
12
atoms/cm
2
(FIG.
5
C). Thus, by increasing the implanted amount of boron into the region in which the memory cell FET is formed, the impurity concentration of the channel region
5
in the memory cell FET and the impurity concentration of the channel region
15
in the peripheral circuits FET are made different from each other Here, the order of the ion implantation shown in FIG.
5
B and the ion implantation shown in
FIG. 5C
can be exchanged.
Thereafter, the pad oxide film
20
and the photoresist
21
formed on the substrate
1
are removed, and a gate oxide film
6
having the thickness on the order of 10 nm is formed on the pri

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