Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-17
2004-07-13
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000, C257S307000, C257S308000, C257S352000, C438S239000, C438S244000, C438S250000, C438S253000, C438S254000, C438S393000, C438S396000, C438S397000
Reexamination Certificate
active
06762445
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device and a method for fabricating the semiconductor memory device and, in particular, to a memory cell structure of a semiconductor memory device that uses a high-&kgr; film or a ferroelectric film.
Recently, embedded-DRAM processes for combining DRAMs with high-performance logic circuits have been put into practical use in multimedia applications requiring large memory capacity and high data transmission speed.
However, since the conventional DRAM process requires high-temperature heating process for formation of a capacitive insulating film of a capacitor functioning as a memory capacitor, it has deficiencies such as worsening an impurity concentration profile of doped layers of a transistor in a high-performance logic circuit. In addition, it is also desirable to avoid the high-temperature heating process as far as possible in a memory single unit process for a DRAM, an FeRAM or the like in realizing miniaturization of a memory cell transistor.
Therefore, it has become indispensable to develop an MIM (metal-insulator-metal) capacitor in which a high-&kgr; film that can be formed at a low temperature and is capable of making a memory size fine is used as the capacity dielectric film of a memory capacitor. As this high-&kgr; film, there is a dielectric film having the perovskite structure such as a BST film ((BaSr)TiO
3
film). On the other hand, Pt that has high oxidation resistance is generally considered prospective as a material for forming a metal electrode of this MIM capacitor. In addition, dielectric films having the perovskite structure such as an SBT film (SrBi
2
Ta
2
O
9
film) and a BTO film (Bi
4
Ti
3
O
12
film) are often used as a ferroelectric film.
However, the conventional MIM capacitor functioning as a memory capacitor has the following problems.
First, when a contact hole is formed directly on a Pt electrode (upper electrode) provided on a capacitive insulating film, a reducing atmosphere or the like at the time when a contact plug is formed is likely to affect properties of the capacitor adversely. This is because oxygen deficiency occurs in a dielectric film due to the reducing atmosphere as, in general, a dielectric film is often an oxide. In particular, when the capacitive insulating film is a high-&kgr; film or a ferroelectric film, the possibility of the occurrence of oxygen deficiency is high. Deterioration in the properties by oxygen deficiency occurs remarkably in a dielectric film having the perovskite structure.
In addition, in a device such as a DRAM in which a Pt electrode is not used, since it is difficult to share existing equipment in a step such as the formation of a contact in a Pt electrode, which is a new material, operation in dedicated equipment becomes necessary. For example, in such a time when a contact hole that reaches a Pt electrode is formed in an interlayer insulating film, since Pt is sputtered when the Pt electrode is exposed, Pt deposits on the wall surface of a chamber, members in the chamber, etc. If this chamber continues to be used, Pt enters an active region or the like of a transistor to affect transistor operations adversely.
SUMMARY OF THE INVENTION
The present invention has been devised in view of the above drawbacks, and it is an object of the present invention to provide a semiconductor memory device having good properties of an MIM capacitor and a method for fabricating the semiconductor memory device by taking measures for inhibiting deterioration of a dielectric film and, at the same time, preventing an electrode material from mixing in a transistor region.
In addition, it is another object of the present invention to provide a semiconductor memory device and a method for fabricating the semiconductor memory device that can reduce manufacturing costs by making dedicated equipment unnecessary.
A semiconductor memory device of the present invention comprises: a memory capacitor that is provided on an insulating layer on a semiconductor substrate and constituted by a lower electrode, an upper electrode and a capacitive insulating film interposed between the lower electrode and the upper electrode; an extension of the upper electrode from the upper electrode of the memory capacitor; a dummy conductor member that is provided such that at least a part of the dummy conductor member comes into contact with an underside of the extension of upper electrode; and upper layer interconnect that is electrically connected to the dummy conductor member.
Consequently, since the upper electrode is connected to the upper layer interconnect via the extension of upper electrode, a dummy lower electrode and the dummy conductor member, it is not unnecessary any more to form a contact hole above the upper electrode and a step in which the upper electrode is exposed to a reducing atmosphere becomes unnecessary. As a result, it becomes unlikely to cause oxygen deficiency in, for example, a capacitive insulating film consisting of BST and deterioration in the properties of the capacitive insulating film can be prevented. In addition, for example, if an electrode is formed of Pt, formation of the lower electrode, the dummy conductor member and the upper electrode is performed by dedicated equipment for Pt film formation. Thus, it becomes unlikely that equipment for the formation of logic circuit elements is contaminated.
The dummy conductor member may consist of a conductor film filling a trench provided in the insulating layer.
The dummy conductor member may further include local interconnect provided on the semiconductor substrate under the insulating layer and a plug that pierces through the insulating layer to electrically connect the extension of upper electrode and the local interconnect.
Since the local interconnect is further provided with a bit line formed below the memory capacitor across the insulating layer and is formed of a conductor film, which is the same as the bit line, a structure suitable for a memory with a capacitor over bit line utilizing the conductor film for the bit line is obtained.
Since at least a part of the extension of upper electrode overlaps the conductor plug when it is viewed two-dimensionally, the upper electrode and the upper layer interconnect are securely connected.
The semiconductor memory device further comprises: an isolating insulating film that is provided on the semiconductor substrate below the insulating layer; a memory cell transistor formed in a region of the semiconductor substrate, the memory cell transistor including a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode there between; local interconnect that is provided on the isolating insulating film and is formed of the same conductor film as the gate electrode; and a conductor plug that pierces through the insulating layer and is connected to the local interconnect. Therefore, a structure that can be applied to both a memory with a capacitor over bit line and a memory with a capacitor under bit line is obtained utilizing a conductor film (a polysilicon film, etc.) for the gate electrode.
The semiconductor memory device further comprises: a memory cell transistor that is provided on the semiconductor substrate and has a gate electrode and doped layers defined within the semiconductor substrate below the gate electrode to horizontally sandwich the gate electrode there between; local interconnect that is formed of another doped layer, which is provided separately from the doped layers on the semiconductor substrate; and a conductor plug that pierces through the insulating layer and is connected to the local interconnect. Therefore, a structure that can be applied to both a memory with a capacitor over bit line and a memory with a capacitor under bit line is obtained utilizing a step for forming source and drain regions.
Since the upper layer interconnect is in contact with the dummy lower electrode, a structure that can be applied to a memory with a capacitor
Mori Yoshihiro
Ogawa Hisashi
Tsuzumitani Akihiko
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Nelms David
Tran Long
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