DRAM memory cell for programmable logic devices

Details DRAM memory cell for programmable logic devices DRAM memory cell for programmable logic devices

1996-11-01

1998-12-08

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

326 41, 365228, 711106, H03K 19177, G11C 700

Patent

active

058475770

ABSTRACT:
A plurality of DRAM cells are used to store the state of the programmable points in a programmable logical device (e.g., a field programmable gate array or FPGA). An individual DRAM cell is used in conjunction with each programmable interconnect point (PIP) within the FPGA to hold a logical state indicating the connectivity state of the PIP. During a refresh cycle, each DRAM memory cell is loaded with its current logical state in order to maintain this state within the PIP. An information store contains duplicate data for each DRAM cell and this duplicate data is supplied and read during the refresh cycle in order to provide each DRAM cell with its proper logical state. In this manner, the refresh cycle does not alter the logic configuration of its associated FPGA DRAM cell. The information store can be a plurality of DRAM cells or the information store can be of non-volatile memory, for instance, read only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), or of non-volatile magnetic storage.

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