DRAM memory cell arrangement

Details DRAM memory cell arrangement DRAM memory cell arrangement

2008-01-22

2008-01-22

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S149000, C365S104000

Reexamination Certificate

active

07321514

ABSTRACT:
The present invention relates to a memory cell arrangement comprising a multiplicity of DRAM memory cells which are arranged in cell rows and cell columns and the selection transistor of which comprises in each case a first gate electrode and also a rear side electrode. The memory cell arrangement contains word lines and also rear side electrode lines which are arranged in each case alternately between adjacent cell columns. The invention provides for in each case the first gate electrodes of adjacent cell columns to be connected to the word line lying between the cell columns and in each case the rear side electrodes of adjacent cell columns to be connected to the rear side line lying between the cell columns. All the rear side lines are held at a constant potential, while for reading from a memory cell that word line is addressed to which the first gate electrode of the memory cell to be read is connected.

REFERENCES:
patent: 5414654 (1995-05-01), Kubota et al.
patent: 6262448 (2001-07-01), Enders et al.
patent: 6638812 (2003-10-01), Schlosser et al.
patent: 6707706 (2004-03-01), Nitayama et al.
patent: 2003/0116784 (2003-06-01), Divakaruni et al.
patent: 2004/0259312 (2004-12-01), Schlosser et al.
patent: 2005/0190617 (2005-09-01), Forbes et al.
B. Goebel et al., “Fully Depleted Surrounding Gate Transistor (SGT) for 70 nm DRAM and Beyond”, 2002 IEEE (4 pgs.).

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