DRAM interface circuits that support fast deskew calibration...

Details DRAM interface circuits that support fast deskew calibration... DRAM interface circuits that support fast deskew calibration...

2006-07-18

2009-06-30

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

Correction for skew, phase, or rate

C713S401000, C713S500000

Reexamination Certificate

active

07555668

ABSTRACT:
A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS) received at an interface of the integrated circuit device. A data capture circuit is also provided. The data capture circuit is configured to capture a plurality of data streams (DQ) associated with the plurality of data strobe signals in a manner that sufficiently reduces skew between the captured data streams so that all of the plurality of data streams may then be reliably captured in-sync with a common clock.

REFERENCES:
patent: 7079446 (2006-07-01), Murtagh et al.
patent: 2005/0066142 (2005-03-01), Bhattacharya et al.
patent: 2006/0200598 (2006-09-01), Janzen
patent: 2007/0006011 (2007-01-01), Martin et al.

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