DRAM including pseudo negative word line

Details DRAM including pseudo negative word line DRAM including pseudo negative word line

2011-08-02

2011-08-02

Ho, Hoai V (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S145000, C365S189150, C365S189160, C365S194000, C365S205000

Reexamination Certificate

active

07990755

ABSTRACT:
For increasing retention time in DRAM, pseudo negative word line scheme is realized such that voltage of a local bit line pair is always higher than that of an unselected word line for applying negative gate voltage, but selected word line is asserted to a pre-determined voltage. For implementing the scheme, swing voltage of the local bit line pair is limited by a write path connecting to a global bit line pair when writing, and the local bit line pair is also limited when reading, because selected local bit line is slightly changed with charge re-distribution and unselected local bit line is at floating state. For minimizing sensing current, a locking signal is generated to cut off a current path from the global bit line pair to a local sense amp. And various alternative circuits are described for implementing the pseudo negative word line scheme.

REFERENCES:
patent: 5715189 (1998-02-01), Asakura
patent: 6426905 (2002-07-01), Dennard et al.
patent: 6456521 (2002-09-01), Hsu et al.
patent: 2010/0182846 (2010-07-01), Kim
A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM in VLSI Circuits, Digest of Technical Papers, May 1993.
A 322 MHz Random-Cycle Embedded DRAM With High-Accuracy Sensing and Tuning, IEEE Journal of Solid-State Circuits, vol. 40, No. 11, Nov. 2005.
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier, IEEE International Solid-State Circuits Conference, pp. 486, 2007.

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