DRAM hierarchical data path

Details DRAM hierarchical data path DRAM hierarchical data path

2007-10-30

2007-10-30

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

C365S189060

Reexamination Certificate

active

11108369

ABSTRACT:
A hierarchical DRAM array, DRAM macro and logic chip including the DRAM macro embedded in the logic. DRAM array columns are segmented with a small number (e.g., 2-64) of cells connected to a local bit line (LBL) in each segment. Each LBL drives a sense device that drives a global read bit line (GRBL). When a cell storing a high is selected, the cell drives the LBL high, which turns the sense device on to drive the GRBL low. Segments may be used individually (as a macro) or combined with other segments sharing a common GRBL.

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