DRAM having SRAM equivalent interface

Details DRAM having SRAM equivalent interface DRAM having SRAM equivalent interface

2006-12-19

2006-12-19

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000

Reexamination Certificate

active

07152150

ABSTRACT:
A semiconductor memory device includes a memory core circuit, a command circuit which receives commands from an exterior of the device at intervals at least as long as a minimum command cycle, a timing generator configured to request a read access to the memory core circuit immediately after inputting of a read command if a command supplied from the exterior to the command circuit is the read command, to perform a read operation on the memory core circuit immediately after the request of the read access if there is no currently performed operation in the memory core circuit, to request a write access to the memory core circuit after data is fixed prior to an end of a command cycle during which a write command corresponding to the write access is entered from the exterior to the command circuit, to perform a write operation on the memory core circuit immediately after the request of the write access if there is no currently performed operation in the memory core circuit, and to control an order of a plurality of accesses if the plurality of accesses conflict with each other with regard to access to the memory core circuit.

REFERENCES:
patent: 6459650 (2002-10-01), Lin
patent: 6484246 (2002-11-01), Tsuchida et al.
patent: 6542959 (2003-04-01), Tabo
patent: 6643732 (2003-11-01), Shih
patent: 6751157 (2004-06-01), Leung
patent: 2002/0138687 (2002-09-01), Yang et al.
patent: 2003/0063512 (2003-04-01), Takahashi et al.

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