Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2002-08-19
2004-11-16
Wojciechowicz, Edward (Department: 2815)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S522000, C438S524000, C438S525000
Reexamination Certificate
active
06818534
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductors, and more particularly to leakage performance in trench DRAM.
2. Discussion of Related Art
In trench DRAM, retention of an electric charge in a cell capacitor is largely a function of various leakage mechanisms. These mechanisms include, for example, a sub-STI leakage and reverse-bias leakage at the buried strap junction.
Referring to
FIG. 1
, the BEST (BuriEd-STrap) cell uses a collar oxide
101
at a top portion of the trench to isolate the capacitor
103
from an access transistor at the silicon (Si) surface. The buried-strap
107
connects a word-line
105
to the capacitor
103
.
FIG. 2
shows a detailed view of the region near the buried-strap
107
.
Referring to
FIG. 2
, an As-doped poly-Si
201
creates the n+ buried-strap junction
107
by outdiffusion of As into single-crystal Si. When outdiffused, the p-dopant helps form a more abrupt junction with improved reverse bias leakage behavior. However, a weakly doped region
203
can form at the top of the collar oxide
101
below the buried-strap junction
107
. Thus, the topography can make it difficult to dope this region, compromising the reverse bias leakage performance of the device.
Therefore, a need exists for a device having improved charge retention through improved reverse bias leakage.
SUMMARY OF THE INVENTION
A semiconductor memory device comprises a trench etched from a substrate below a shallow trench isolation and a doped collar oxide. The device further comprises a buried-strap junction formed adjacent to the shallow trench isolation and above the collar oxide, and a channel stop formed below the buried-strap junction, wherein a junction between the channel stop and the buried-strap junction is formed in the substrate.
The collar oxide is a boro-silicate glass. The boro-silicate glass comprises about 6% Boron by weight.
The oxide collar is p-doped. The channel stop comprises a region of p-doped substrate.
According to embodiment of the present invention, a method of manufacturing a semiconductor memory device comprises providing a substrate, forming a trench in the substrate, wherein the trench comprises sidewalls, and forming a layer of poly-silicon in a bottom portion of the trench. The method further comprises forming a collar on the sidewalls of the trench, forming a second layer of poly-silicon in a second bottom portion of the trench, and removing a top portion of the collar. The method forms a third layer of poly-silicon in a third bottom portion of the trench, wherein the third layer of poly-silicon is in contact with a top portion of the collar, forms an isolation region in a portion of the substrate, wherein the isolation region caps the trench, and outdiffuses dopants from the third layer of poly-silicon and the collar into the substrate.
The method further comprises planarizing the surface of the substrate after forming the isolation region, wherein the substrate comprises a silicon layer and a top nitride layer.
The outdiffusion of dopants from the third layer of poly-silicon forms a buried-strap junction and the outdiffusion of dopants from the collar forms a channel stop.
According to an embodiment of the present invention, a semiconductor memory device comprises a buried-strap trench cell capacitor comprising a collar oxide deposited on a portion of a trench sidewall and a channel stop, outdiffused into a substrate and position substantially beneath a buried-strap of the buried-strap trench cell capacitor.
REFERENCES:
patent: 4704368 (1987-11-01), Goth et al.
patent: 6310375 (2001-10-01), Schrems
Davis Jonathan Philip
Rusinko, Jr. Stephen M.
Infineon Technologies Richmond LP
Wojciechowicz Edward
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