DRAM for high-speed data access

Details DRAM for high-speed data access DRAM for high-speed data access

2007-10-02

2007-10-02

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

For multiple memory modules

C711S105000

Reexamination Certificate

active

10330482

ABSTRACT:
A DRAM with a general interleaving scheme for data input/output uses a normal bank structure. The DRAM provides a high-performance without consideration of a data access pattern. In order to implement the high-performance, the DRAM includes a plurality of normal banks, at least one cache bank, which has the same data access scheme with the normal banks, for selectively storing data with a normal bank selected at a read mode and a controller for controlling the access to the cache bank and the selected normal bank when continuous read commands are occurred to the selected normal bank.

REFERENCES:
patent: 6229752 (2001-05-01), Ayukawa et al.
patent: 2001/0038567 (2001-11-01), Ishikawa
patent: 2003/0204667 (2003-10-01), Ji et al.
patent: 06-348593 (1994-12-01), None

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