DRAM fabricated on a silicon-on-insulator (SOI) substrate...

Details DRAM fabricated on a silicon-on-insulator (SOI) substrate... DRAM fabricated on a silicon-on-insulator (SOI) substrate...

2000-08-31

2002-10-15

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

On insulating substrate or layer

C438S149000, C438S266000, C438S587000, C257S296000, C257S347000, C257S350000

Reexamination Certificate

active

06465331

ABSTRACT:

TECHNICAL FIELD
The invention relates to dynamic random access memories (“DRAMs”), and more particularly to a folded digit line array DRAM having bi-level digit lines.
BACKGROUND OF THE INVENTION
Early DRAMs were manufactured with an “open digit line” architecture, in which a first digit line of a complementary pair extended from a respective sense amplifier through a first array, and a second digit line of the complementary pair extended from the sense amplifier through a second array. Therefore, in these early DRAMs, the memory cells in each column of the first array were selectively coupled to one digit line, and the memory cells in the corresponding column of the second array were selectively coupled to its complementary digit line. An advantage of this open digit line architecture is that it allows memory cells to occupy a relatively small area, i.e., 6F
2
, where “F” is the minimum feature size of a semiconductor process. Unfortunately, the digit lines in an open digit line architecture are susceptible to picking up noise. As a result, a “folded digit line” architecture was developed.
FIG. 12
is a functional block diagram of a conventional memory-cell array
1200
having a folded-digit line architecture. The array
1200
includes a plurality of memory cells
1202
arranged in rows and columns, each memory cell including an access transistor
1204
and storage capacitor
1206
, as shown for one cell. Each memory cell
102
in a respective row is coupled to a corresponding word line WL and each memory cell in a respective column is coupled to one of a pair of complementary digit lines DL, DL*. A plurality of sense amplifiers
1208
are coupled to respective pairs of complementary digit lines DL, DL*. Each memory cell
1202
includes an access transistor
1204
coupled to the word line WL of the corresponding row, and when activated the access transistor the storage capacitor
1206
to one of the digit lines DL, DL* in the corresponding column.
In a folded digit line architecture, both complementary digit lines extend from a sense amplifier through the same array substantially in parallel with each other. Since the digit lines are parallel to each other for substantially their entire lengths, they pick up the same noise signals, thus allowing a sense amplifier to which they are coupled to have good common mode noise rejection. DRAMs having a folded digit line architecture are thus less susceptible to noise. Unfortunately, the requirement that an additional digit line extend through the array increases the size occupied by each memory cell. In fact, memory cells in a folded digit line architecture have a minimum size of 8F
2
.
Attempts have been made to reduce the minimum size of folded digit line memory cells by vertically spacing the digit lines in each complementary pair rather than horizontally spacing them apart at the same level. By spacing the digit lines vertically, the area occupied by a memory cell can be reduced to
6
F . Unfortunately, it has been difficult to fabricate bi-level digit lines because of the large number of components that must be formed on the surface of a semiconductor substrate. The difficulty in fabricating bi-level digit lines in DRAMs having a folded digit line architecture has prevented their widespread use. As a result, folded digit line DRAMs have generally been significantly larger than open digit line DRAMs of the same capacity, thus making folded digit line DRAMs more expensive. Therefore, a need exists to be able to more easily manufacture DRAMs having bi-level digit lines so that DRAMs having folded digit line architectures can be manufactured at less cost.
SUMMARY OF THE INVENTION
A DRAM array having a folded digit line architecture is fabricated on a silicon-on-insulator substrate. The array includes bi-level digit lines that are fabricated on opposite sides of a silicon portion of the substrate. As a result, the digit lines for each digit line pair may occupy the same footprint, thus allowing the array to be relatively small. Access transistors coupled to each of a plurality of memory cells may be coupled to either of the digit lines, or they may be alternately coupled to the digit lines. The digit lines of each pair are preferably “twisted” at least once as they extend through the array so that they have the same electrical characteristics.


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