DRAM enhanced processor

Details DRAM enhanced processor DRAM enhanced processor

1998-10-05

2002-11-19

Patel, Ramesh (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S002000, C700S004000, C700S005000, C700S117000, C711S105000, C711S112000, C716S030000, C716S030000, C716S030000, C365S149000, C365S230030, C712S001000, C712S010000, C712S016000

Reexamination Certificate

active

06484065

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates to digital signal processing (DSP) and, more particularly, to the integration of processors and memory.
BACKGROUND OF THE INVENTION
In recent years we have been witness to many advances in VLSI (very Large Scale Integration) technology. Minimum feature sizes on integrated circuits (ICs) continue to shrink, permitting dramatic improvements in processing speeds, reduced power consumption and increased functional density. Due to higher functional integration, new processing architectures for microprocessors (MPUs) and digital signal processors (DSPs) achieve higher performance by employing such techniques as VLIW (Very Long Instruction Word) and SIMD (Single Instruction Multiple Data). Other improvements in integrated circuit fabrication technology have made much denser RAMs possible, and have brought forth new memory architectures that promise substantial improvements in memory access efficiency for certain applications.
Traditionally, memory chip architecture and fabrication techniques have been cost and volume driven, while processing architectures and fabrications techniques have been performance and speed driven. New and emerging applications of MPU's and DSP's tend to require massive high-speed, data arrays which require massive high-speed locally-connected memories. The traditional design goals for memories and processors have resulted in a few performance and configuration “gaps” between DSP and memory functionality:
Operating Frequency: Although clock frequencies for DSPs or MPUs are approaching 500 MHz, the maximum access times for RAM memories is only approaching 150 MHz. Hence, a typical DSP or MPU may be capable of processing and execution speeds three times faster than the RAM to which it must connect.
Data Bus and Address Bus width: DSPs and MPUs, being performance-driven architectures, have moved rapidly towards very-wide address and data buses. Memories on the other hand, particularly Dynamic RAM architectures, however, tend to be rather “stingy” with package pins, and have moved towards such techniques as minimizing pinout by multiplexing the address bus, which limits their performance and tends to complicate interface circuitry.
To overcome these performance and configuration gaps between memory architecture and processing architecture:, memory designers have devised a number of improvements to the external interfaces of RAM memories. Among the improvements that have been made are: Rambus DRAM (RDRAM), Sync-Link and Synchronous Graphics RAM (SGRAM). However, even these improved DRAMs have some important, limiting constraints on their usage:
DRAM is typically only available in huge binary multiple increments (e.g, 4 Mbytes, 8 Mbytes, 16 Mbytes, etc.). If “HUGE_INCREMENT” plus 1 byte is required for a particular application, the designer is essentially “forced” into using double (twice) “HUGE_INCREMENT” amount of memory, and the remaining memory is wasted.
Cost is also a prevalent problem, and relates to memory granularity and architecture. For some applications, the size of general purpose RAM is not optimum. An example is when an application requires 4.2 MB of application specific memory and only 4M and 16 MB RAM are available. A 4.2 MB application specific memory module could cost less than two 4 MB RAMs or one 16 MB RAM if it were to be produced in sufficiently large volume to cover the development and production costs.
In an attempt to address these problems directly, there has been some research on the integration of a processor and DRAM onto a single chip. Most of this work consists of integrating the two functions (DRAM and processor) by using the fabrication process of one function and adapting the design of the other function to fit, for example by integrating an MPU function onto a DRAM process, by altering the multi-layer metal process of a processor to use the polysilicon-connected fabrication process of a DRAM. Unfortunately, this tends to adversely impact the processor's performance, since polysilicon connection are inherently more resistive than metal interconnection layers, resulting in “slower” circuits due to RC (resistive-capacitive) delay from the interaction between the polysilicon connection and on-chip parasitic capacitances.
Evidently, there is a need for a DSP or MPU with Embedded DRAM which is cost-effective and performs better than conventional DSP/DRAM or MPU/DRAM pairings.
DISCUSSION OF THE PRIOR ART
The following documents, all of which are US patents, all of which are incorporated by reference herein, disclose various techniques having some relevance to the present invention.
U.S. Pat. No. 5,663,570 (September 1997) discloses a high-frequency wireless communication system on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. See also related U.S. Pat. No. 5,492,857 (February 1996).
U.S. Pat. No. 5,642,295 (June 1997) discloses systems utilizing a single chip microcontroller having non-volatile memory devices and power devices.
U.S. Pat. No. 5,634,108 (May 1997) discloses a single chip processing system utilizing general cache and microcode cache enabling simultaneous multiple functions.
U.S. Pat. No. 5,625,836 (April 1997) discloses SIMD/MIMD processing memory element (PME). Eight processors on a single chip have their own associated processing element, significant memory, and I/O, and are interconnected with a hypercube-based topology. Particular attention is directed to column 22 lines 54-55 of this patent, wherein it is stated (with reference to
FIG. 2
of the patent) that “we combine both significant memory and I/O and processor into a single chip.” As also described therein (column 20, lines 49-50), our device is a 4 MEG CMOS DRAM believed to be the first general memory chip with extensive rom for logic.” See also related U.S. Pat. No. 5,588,152 (December 1996) which discloses advanced parallel processor including advanced support hardware.
U.S. Pat. No. 5,506,437 (April 1996) discloses a microcomputer with high density RAM in separate isolation well on a single chip. See also related U.S. Pat. No. 5,491,359 (February 1996).
U.S. Pat. No. 5,473,573 (December 1995) discloses single chip controller-memory device and a memory architecture and methods suitable for implementing same.
U.S. Pat. No. 4,942,516 (July 1990) discloses single chip integrated circuit computer architecture.
U.S. Pat. No. 4.734,856 (March 1988) discloses autogeneric system.
GLOSSARY
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used in the description contained herein:
A/D: Analog-to-Digital (converter).
ALU: Arithmetic Logic Unit.
ASIC: Application-Specific Integrated Circuit.
bit: binary digit.
byte: eight contiguous bits.
CAM: Content-Addressable Memory.
CMOS: Complementary Metal-Oxide Semiconductor.
CODEC: Encoder/De-Coder. In hardware, a combination of A/D and D/A converters. In software, an algorithm pair.
CPU: Central Processing Unit.
D/A: Digital-to-Analog (converter).
DRAM: Dynamic Random Access Memory
DSP: Digital Signal Processing (or Processor)
EEPROM: Also E2PROM. An electrically-erasable EPROM.
EPROM: Erasable Programmable Read-Only Memory.
Flash: Also known as Flash ROM. A form of EPROM based upon conventional UV EPROM technology but which is provided with a mechanism for electrically pre-charging selected sections of the capacitive storage array, thereby effectively “erasing” all capacitive storage cells to a known state.
FPGA: Field-Programmable Gate Array g: or (giga), 1,000,000,000
Gbyte: gigabyte(s).
GPIO: General Purpose Input/Output.
HDL: Hardware Description Language.
IC: Integrated Circuit.
I/O: Input/Output.
IEEE: Institute of Electrical and Electronics Engineers
JPEG: Joint Photographic Experts Gro

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