DRAM (dynamic random access memory) cells

Details DRAM (dynamic random access memory) cells DRAM (dynamic random access memory) cells

2007-07-19

2010-02-02

Malsawma, Lex (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257SE27093

Reexamination Certificate

active

07655967

ABSTRACT:
A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

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