Static information storage and retrieval – Read/write circuit – Flip-flop used for sensing
Reexamination Certificate
2001-08-14
2002-09-10
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Flip-flop used for sensing
C365S203000
Reexamination Certificate
active
06449202
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a DRAM direct sensing scheme, and more particularly pertains to a DRAM direct sensing scheme which relies upon the pFET threshold voltage of a pFET device to detect a signal development level with a significant reduction in the number of devices in the primary sense amplifier.
In the design of DRAMs, the direct sensing scheme is emerging and becoming more popular because future DRAMs need to use a lower bitline voltage. This restriction is applied from both scaling and performance points of view. From the scaling point of view, the device sizes need to be reduced to obtain a higher density of the memory. This requires reduced operation voltages to meet the reliability specifications and basic device performance requirements like the device threshold voltage Vt roll-off. Performance requirements such as speed require a lower bit-line high voltage Vblh to obtain more overdrive of array devices with a limited word line voltage Vpp. The word line voltage Vpp is limited by the gate oxide thickness, which is reduced as the device size is reduced. This is especially true for the write back operation.
If Vblh is reduced, however, the conventional 1/2 Vblh sensing scheme adopted in most DRAMs on the market is not practical to implement due to its low signal development. This encourages the direct sensing scheme.
Simultaneously, lowering the operating voltages, especially lowering Vpp, makes it more difficult to writeback “high” data into the cell. This is based upon the fact that the back bias of the array device increases as “high” data is written into the cell, which increases Vt and reduces the overdrive of the array device. This adversely impacts the writeback time of the “high” cell, which limits high speed applications.
One way to solve the above problem is to only sense “low” with a direct sensing scheme and a VDD precharge level. One problem with this scheme, however, is the very small signal difference between “low” and “high” cells, because the cell voltage of the “high” cell is not well defined. Therefore, one approach is to amplify the developed signal.
Because this is a DRAM, it is necessary to writeback the data after reading it. The read operation in a DRAM is inherently destructive of the data because once the transistor for a memory cell is switched on, the charge on the memory cell capacitator dissipates onto the bitline and eliminates its once readable logic level. Therefore, conventional DRAMs employ a writeback cycle as part of the read operation. With a conventional sense amplifier circuit, there is a delay between the time the accessed sense amplifier detects data from the memory cell and the time the data can be fully written back to the data cell, because of the extra loading on the bit line of the data line (DQ) which carries the data out of the primary sense amplifier. By employing a sense amplifier which terminates the bit line into the gate of the transistor, the bit line is decoupled from the loading of the DQ line which both reduces the time sense data, and also improves the ability to sense the data correctly.
2. Discussion of the Prior Art
For applications which require a fast random access time, the traditional CMOS cross-coupled sense amp has limitations in both sensing time and writeback. The writeback limitation can be avoided by performing a technique such as a destructive read operation (Disclosure: Toshi Kirihata et al). The sensing time limits the memory cycle time because the bitline signal must be amplified and transferred to a dataline. Sensing a small bitline signal and transferring it to a digital data line with traditional techniques requires more than 5 ns. Hence the need for higher speed direct sense techniques.
1) Conventional cross-coupled sense amps without reference cells require a VDD/
2
bitline voltage precharge. When the sense amps are set, positive moving bitlines couple unselected wordlines upward, which increases cell leakage.
2) A conventional direct sensing scheme with a current mirror sense amplifier uses a bitline pair and a data line pair per bit. A current mirror sense amplifier requires a large design space, resulting in poor density and an expensive solution.
3) Some DRAM macros require sensing and reading out of every bitline signal, rather than decoding a portion of the senseamps and reading out a subset. This requires a read/write head which can couple the sense amp data to external datalines without creating a read disturb. A read disturb occurs when a precharged dataline is connected to a sense amp. This effect is reduced if a pair of datalines are connected to both true and complement sense amp nodes. In dense DRAM macros where every cell along a wordline must be outputted, there is a large area penalty to operate with differential datalines and their associated circuitry. In some cases, it is impossible to arrange a differential data line pair for each bitline pair because of design rule constraints, which makes it difficult or impossible to use a conventional direct sensing scheme.
4) As technology advances to smaller lithographies, voltages must be scaled to lower levels to reduce oxide stress. It is known that the device threshold voltage Vt does not scale efficiently with power supply, and so overdrive is lost on FETs. VDD/
2
sensing schemes must operate with very low overdrive at low power supplies, and hence suffer a large degradation in sensing speed as the device Vt increases at low temperatures.
5) Testing of on-chip DRAM macros is difficult because of pattern sensitivities. One advantage of the sensing scheme of the present invention is that only every other bitline is active, so that alternating bitlines can be held at AC ground to eliminate line to line coupling effects. The increased bitline signal also increases sensing margin.
6) It is preferable to maintain the same polarity (even number of signal inversions) between the bitline BL signal and the dataline (DQ) signal. If this condition is met, the primary sense amplifier can be employed to write-back data into the storage capacitor.
7) It is preferable to minimize logical “glitches” on the datalines (DQs) so that dynamic logic can be used to control the data buses. Here, a “glitch” is defined as a signal waveform that will cause a logical error if it is an input to a dynamic logic gate.
Atsumi et al (ISSCC 2000, p276) discusses a direct sensing scheme for EEPROM with a sense amplifier using an NFET. This requires a reference bitline, and no feedback loop exists to writeback data to the bitline (because this is an EEPROM).
Suh et al (J. Solid State Circuits, 31, 1025 (1996)) discusses a direct sensing scheme for a DRAM which needs a reference voltage to power the rewrite amplifier and uses an NFET for the sensing.
FIG. 1
illustrates a typical prior art direct sensing circuit using both a direct sensing block and also a cross-coupled sensing block. The direct sensing circuit block consists of a read portion
104
and a write portion
105
. The read portion is triggered by a read control RE. The write portion is triggered by a write control WE. A pair of switches N
10
and N
11
are provided to selectively connect the Bitline pairs to the sense amplifier via a control MUX. Another pair of switches N
23
and N
24
is provided to selectively connect the sense amplifier with a pair of datalines DQ and bDQ. The direct sensing block includes two further pull down NMOS devices N
17
and N
18
. When the complementary signals are developed on the Bitline pair and are being transferred to the sense amplifier, the signals are first amplified by a cross-coupled sense amplifier which is formed by a p-latch
103
, and an n-latch
102
. When the read signal is triggered, the direct sensing devices further enhance and develop the signal.
FIG. 1
shows an exemplary 1/2 Vdd sensing scheme. After sensing, the pair of bit-lines are restored back to 1/2 Vdd level via a precharge and equalization circuit
101
formed by three nMOS devices, N
12
, N
13
and N
14
. The wri
Akatsu Hiroyuki
Hsu Louis L.
Stephens Jeremy K.
Storaska Daniel W.
Neff, Esq. Daryl K.
Scully Scott Murphy & Presser
Tran M.
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