Dram device with improved memory cell reliability

Details Dram device with improved memory cell reliability Dram device with improved memory cell reliability

1997-10-09

2002-10-15

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S408000

Reexamination Certificate

active

06465851

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device for improving a reliability of memory cells in a DRAM (Dynamic Random Access Memory) and a method of manufacturing the same.
2. Description of the Background Art
As shown in
FIG. 23
, a DRAM has one-transistor and one-capacitor structure including one MOS transistor
27
and one capacitor
28
. A voltage equal to or higher than a predetermined threshold voltage is applied to a gate electrode of the MOS transistor so that electric charges are accumulated in or discharged from the capacitor. Through these operations, data is held, written or read.
A conventional method of manufacturing a DRAM will be described below with reference to Japanese Patent Laying-Open No. 2-143456 (1990).
Referring to
FIG. 24
, an element isolating and insulating film
2
is formed on a silicon substrate
1
by a trench isolating method. Element isolating and insulating film
2
defines a plurality of regions for forming MOS transistors and others on silicon substrate
1
. A gate oxide film
3
is formed by a thermal oxidation method. A polycrystalline silicon film
4
and a silicon oxide film
5
are formed. Gate electrode portions
6
are formed by anisotropic etching effected on polycrystalline silicon film
4
and silicon oxide film
5
masked with a predetermined photoresist. Ion implantation is performed to from n
−
source/drain regions
7
a
,
7
b
,
7
c
and
7
d.
Referring to
FIG. 25
, a side wall
8
is formed on a side surface of each gate electrode portion
6
. An ion implantation method is performed to form n
+
-source/drain regions
9
a
,
9
b
,
9
c
and
9
d
. Thereby, source electrode portions
10
a
and
10
b
as well as drain electrode portions
11
a
and
11
b
are formed.
Referring to
FIG. 26
, a chemical vapor deposition method or the like is performed to form epitaxial silicon layers
12
a
and
12
b
only on source electrode portions
10
a
and
10
b
. Epitaxial silicon layers
12
c
and
12
d
are formed on only drain electrode portions
11
a
and
11
b
. Epitaxial silicon layers
12
a
,
12
b
,
12
c
and
12
d
thus formed have top surfaces located higher than tops surfaces of silicon oxide films
5
of the gate electrode portions, and protrude over side walls
8
and element isolating and insulating film
2
.
Referring to
FIG. 27
, an insulating film
13
a
is formed by a chemical vapor deposition method or the like.
Referring to
FIG. 28
, bit line contacts
14
and bit lines
15
are formed. An insulating film
13
b
covering bit lines
15
is formed on insulating film
13
a
. Storage node contacts
16
a
and
16
b
as well as storage nodes
17
a
and
17
b
are formed. A cell plate
19
is formed on storage nodes
17
a
and
17
b
with a high capacity insulating film layer
18
therebetween. Storage node
17
a
, high capacity insulating film layer
18
and cell plate
19
form one capacitor
20
. Thereafter, metal interconnections and others are formed on capacitor
20
with an interlayer insulating film layer therebetween. In the foregoing manner, the semiconductor device is completed.
The above method of manufacturing the semiconductor device suffers from the following problem. First, as shown in
FIG. 29
, epitaxial silicon layers
12
a
and
12
b
are gradually formed only on n
+
-source/drain regions
9
b
and
9
c
after the step in
FIG. 25
, respectively.
As shown in
FIG. 30
, epitaxial silicon layers
12
a
and
12
b
continuously grow over surfaces of element isolating and insulating film
2
and side wall
8
. Finally, as shown in
FIG. 31
, epitaxial silicon layers
12
a
and
12
b
cover the entire surface of side wall
8
and a part of the upper surface of element isolating and insulating film
2
.
It has been reported in Journal of Crystal Growth
111
(1991), pp. 860-863 that polycrystalline silicon pieces
21
are generated on element isolating and insulating film
2
, silicon oxide film
5
and others when the thicknesses of epitaxial silicon layers
12
a
and
12
b
exceed a predetermined value.
According to this reference, a material gas of, e.g., Si
2
H
6
collides with the surface of the silicon oxide film during growth of the epitaxial silicon layer, and a part of the material gas decomposes into adatoms on the surface of the silicon oxide film. When the surface of the silicon oxide film is covered by these adatoms to a certain extent, polycrystalline silicon grows around adatoms serving as nuclei. Thus, the grown polycrystalline silicon changes into polycrystalline silicon pieces.
In typical formation of the epitaxial silicon layer, it can be estimated that this threshold thickness is about 150 nm. Lateral protrusion Gs of about 60 nm occurs at this time as shown in FIG.
31
.
In the case of the 1-gigabit DRAM, it is estimated that gate electrode portion
6
has a height Hg of about 200 nm and an element isolating and insulating film
2
has a width Wt of about 200 nm. In this case, a thickness equal to or larger than threshold thickness Ts is required for forming epitaxial silicon layers
12
a
and
12
b.
If film thickness Ts is 200 nm, lateral protrusion Gs is about 80 nm. If the element isolating width is 200 nm, a space Ds of only about 40 nm is left between epitaxial silicon layers
12
a
and
12
b
. Polycrystalline silicon pieces
21
are generated on element isolating and insulating film
2
between epitaxial silicon layers
12
a
and
12
b.
If polycrystalline silicon pieces
21
thus generated are in contact with each other and are also in contact with epitaxial silicon layers
12
a
and
12
b
(i.e., in the case A), neighboring epitaxial silicon layers
12
a
and
12
b
are short-circuited together in this step.
In the other cases including a case B that some of polycrystalline silicon pieces
21
generated in the above step are spaced from the other polycrystalline silicon pieces, neighboring epitaxial silicon layers
12
a
and
12
b
are electrically insulated from each other for the time being.
In a next step, insulating film
13
a
is formed over neighboring epitaxial silicon layers
12
a
and
12
b
. Generally, in processing of forming an insulating film covering a portion between two neighboring patterns, the insulating film may not cover the above portion and a so-called void may be formed if a space between the neighboring convex patterns is relatively small. Particularly, in the case of a 1-gigabit DRAM, the epitaxial silicon layer has film thickness Ts of about 200 nm, and space Ds of about 40 nm is left between neighboring epitaxial silicon layers
12
a
and
12
b
as already described. Therefore, an aspect ratio between neighboring epitaxial silicon layers
12
a
and
12
b
is about
5
, so that a void is very liable to be generated.
As shown in
FIG. 32
, if a void is formed between neighboring epitaxial silicon layers
12
a
and
12
b
, epitaxial silicon layers
12
a
and
12
b
, which were electrically insulated from each other, e.g., in the foregoing case B, may be short-circuited due to polycrystalline silicon pieces
21
which are present in the void and are brought into contact with each other due to some reasons after mounted in a product.
If a void is not formed, and particularly in the case B or the like, each polycrystalline silicon piece is buried in the insulating film, so that neighboring epitaxial silicon layers
12
a
and
12
b
are electrically insulated from each other. In the case A, however, the neighboring epitaxial silicon layers remain in the short-circuited state even if each polycrystalline silicon piece is buried in the insulating film.
As already described, a plurality of polycrystalline silicon pieces are generated during formation of the epitaxial silicon layers, so that the neighboring epitaxial silicon layers may be short-circuited together through the plurality of polycrystalline silicon pieces. Due to presence of the void, the neighboring epitaxial silicon layers may be further s

Affiliated with

Also associated with

Rating

Dram device with improved memory cell reliability does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Dram device with improved memory cell reliability, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Dram device with improved memory cell reliability will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2939609