DRAM device having a memory cell array of a divided bit line typ

Details DRAM device having a memory cell array of a divided bit line typ DRAM device having a memory cell array of a divided bit line typ

1991-03-22

1993-10-05

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, 257908, 257910, 257911, H01L 2968, H01L 2978, H01L 2992

Patent

active

052508315

ABSTRACT:
A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines. Transfer gate transistors (4) in the memory cells have source/drain regions (11 and 13) formed by means of self-alignment with respect to the word lines. Thus, controllability of channel lengths of the transfer gate transistors in the memory cells is improved.

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patent: 4990980 (1991-02-01), Wada
patent: 5010379 (1991-04-01), Ishii
"Technology, The Wild Card", Electronics, Sep. 1989, pp. 61-63, Cole.
"A 1Mb DRAM with a Folded Capacitor Cell Structure", 1985 IEEE ISSCC Digest of Technical Papers, Feb. 1985, pp. 244-245, Horiguchi et al.

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