DRAM device comprising a stacked type capacitor and a method of

Details DRAM device comprising a stacked type capacitor and a method of DRAM device comprising a stacked type capacitor and a method of

1993-06-18

1994-06-21

Clawson, Jr., Joseph E.

Static information storage and retrieval

Systems using particular element

Capacitors

257306, G11C 1124

Patent

active

053233433

ABSTRACT:
A DRAM according to the present invention comprises a memory cell array having memory cells constituted by one transfer gate transistor (10) and a capacitor (11), and a peripheral circuit having a MOS transistor (45a) with the LDD structure. At least the source/drain region (19) connected to the capacitor of the transfer gate transistor is formed of a low concentration impurity region (19a). The low concentration impurity region has an impurity concentration substantially equal to that of the low concentration source/drain region (31) of the LDD MOS transistor of the peripheral circuit. The low concentration/drain region of the transfer gate transistor is formed by masking the surface thereof at the time of the high concentration ion implantation step for high concentration source/drain formation of the MOS transistor of the peripheral circuit. By omitting the high concentration ion implantation step, the substrate deficiency of the source/drain region of the transfer gate transistor is eliminated to suppress leakage of the charge from the capacitor.

REFERENCES:
patent: 4922312 (1990-05-01), Coleman et al.
patent: 5006481 (1991-04-01), Chan et al.
patent: 5017982 (1991-05-01), Kobayashi
patent: 5063425 (1991-11-01), Yamauchi et al.
patent: 5065201 (1991-11-01), Yamauchi
patent: 5089192 (1992-03-01), Coleman et al.
patent: 5089869 (1992-02-01), Matsuo et al.
patent: 5103285 (1992-04-01), Furumura et al.

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