DRAM device and refresh control method therefor

Details DRAM device and refresh control method therefor DRAM device and refresh control method therefor

2005-09-20

2005-09-20

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S105000, C711S162000, C711S167000, C713S323000, C713S324000

Reexamination Certificate

active

06948029

ABSTRACT:
A DRAM (dynamic random access memory) device has: DRAM with a self-refresh function; a DRAM controller for controlling the DRAM; a timer built in or externally connected to the DRAM controller; and CPU for controlling the whole device. In the DRAM device, the DRAM controller monitors access from the CPU to the DRAM and, when there is no access to the DRAM within the time set in the timer, the DRAM controller switches a refresh mode to the self-refresh mode.

REFERENCES:
patent: 5805910 (1998-09-01), Lee et al.
patent: 6229749 (2001-05-01), Cowles et al.
patent: 6311250 (2001-10-01), Kishino
patent: 6334167 (2001-12-01), Gerchman et al.
patent: 6542959 (2003-04-01), Tabo
patent: 6546472 (2003-04-01), Atkinson et al.

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