DRAM controller that forces a refresh after a failed refresh...

Details DRAM controller that forces a refresh after a failed refresh... DRAM controller that forces a refresh after a failed refresh...

2011-08-09

2011-08-09

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711SE12003

Reexamination Certificate

active

07996603

ABSTRACT:
A refresh controller transmits two refresh request signals of a first request signal which indicates a time at which a refresh operation of a DRAM may be performed and a second request signal which indicates a time at which a refresh operation of the DRAM must be performed, to an arbitrator. On the other hand, also transfer request signals each of which requests a data transfer are transmitted from plural data transfer parts, respectively, to the arbitrator. If no transfer request signal is input when a first request signal is input to the arbitrator, a refresh operation of the DRAM is performed. As a result, a refresh operation is performed when the crowding level of a bus is relatively low. This improves an efficiency in a data transfer.

REFERENCES:
patent: 6754786 (2004-06-01), Suzuki et al.
Aaron Rice, (Curiosities), Project Galactic Guide, Feb. 10,1997, http://www.galactic-guide.com/articles/8R69.html.

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