DRAM control circuit

Details DRAM control circuit DRAM control circuit

1994-11-22

1995-12-26

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Data refresh

36518907, 365230, 365 02, 3652385, G11C 11401, G11C 700

Patent

active

054793726

ABSTRACT:
A DRAM control circuit, having a second counter 12 which counts the number of times of generation of a refresh request signal generated by a first timer circuit 100, a set value register 13 which holds the maximum number of reservations for refreshing a DRAM 52, and a second comparator 14 which compares the count value of the counter 12 and a value held by the set value register 13, which cancels high-speed page mode and refreshes the DRAM 52 in a predetermined procedure only at a time when the second comparator 14 detects coincidence between the count value of the second counter 12 and a value held by the set value register 13. This configuration enables it to limit refreshing during high-speed page mode, while achieving a DRAM control circuit capable of operating in high-speed page mode more efficiently.

REFERENCES:
patent: 5021951 (1991-06-01), Baba
patent: 5295109 (1994-03-01), Nawaki
patent: 5313428 (1994-05-01), Inoue
patent: 5347491 (1994-09-01), Kagami

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