DRAM concurrent writing and sensing scheme

Details DRAM concurrent writing and sensing scheme DRAM concurrent writing and sensing scheme

2008-05-20

2008-05-20

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Complementing/balancing

C365S226000, C365S189080, C365S205000

Reexamination Certificate

active

07376027

ABSTRACT:
This invention discloses a write-sensing circuit for semiconductor memories comprising a first and a second local bit-lines (BLs) forming a complementary BL pair, a first and a second global bit-lines (GBLs) forming a complementary GBL pair, and at least one switching circuit controlled by the first and second GBLs and controllably coupling a predetermined power supply source to the first and second BLs, separately, wherein when the first and second GBLs are asserted during a write operation, the switching circuit couples only one of the first and second BLs to the predetermined voltage supply source.

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