DRAM COB bit line and moat arrangement

Details DRAM COB bit line and moat arrangement DRAM COB bit line and moat arrangement

1996-12-20

1998-03-31

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257296, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

057341842

ABSTRACT:
A DRAM uses arcuate moats 18 and wavy bit lines 28, 30 for the array of memory cells. A bit line contact 20 occurs at the apex of the moat and storage node contacts 22, 24 occur at the ends of legs 40, 42 extending from the apex. The wavy bit lines have alternating crests 32, 36 and troughs 34, 38. The bit lines are arranged over the moats with the troughs of each bit line overlying and contacting the apexes of each moat and the crests avoiding any moat. The crests and troughs of the bit lines are offset from one another. In a half-pitch pattern, the troughs of one bit line lie adjacent to the crests of the next bit line. The moats are concave between the legs and the angle between the legs is between about 140 and 170 degrees. The angle between the crests and troughs of the bit lines is between about 110 and 160 degrees. In one embodiment, the central portion 70 between the areas surrounding the storage node contacts is about 10% wider than the areas surrounding the storage node contacts.

REFERENCES:
patent: 5140389 (1992-08-01), Kimura et al.
patent: 5309386 (1994-05-01), Yusuki et al.
patent: 5578849 (1996-11-01), Tadaki et al.
IBM Tech Discl, "Low Temp. Buried Source Isolation Region . . . ", vol. 30 No. 9 Feb. 1988, pp. 164-168.

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