Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-07-26
2002-05-14
Tu, Christine T. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S201000
Reexamination Certificate
active
06389564
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a memory and its testing method, and more particularly, to a memory having test units and its testing method.
2. Description of the Prior Art
The prior art memory and its testing method must use a test machine for writing data into the memory and then reading out the data to compare with the original data. The prior art method can only test one, four or eight bits on one word line at a time. Generally, there are millions of memory units in one memory and much time is spent writing data into memory and reading it out for testing. Therefore, a lot of time is required to test all memory units which increases the production costs of the memory.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a memory and its testing method to test the memory more efficiently.
Briefly, in a preferred embodiment, the present invention provides a memory circuit comprising:
a plurality of word lines;
a plurality of bit line groups each having two bit lines;
a memory unit connected between each of the word lines and one bit line of each of the bit line groups wherein the word line connected to the memory unit is used for initiating the memory unit to input or output a binary data bit through the bit line connected to the memory unit;
a plurality of writing units, each of the writing units comprising two output ports separately connected to the two bit lines of one of the bit line groups for simultaneously outputting two opposite binary data bits;
a plurality of testing units, each of the testing units comprising at least two input ports separately connected to an output port of one writing unit and the bit line connected to the output port, and a test circuit for generating a test signal according to the inputs from the two input ports;
a plurality of bit line switches, each of the bit line switches being connected between one output port of each writing unit and the bit line connected to the output port for controlling the output from the output port to the bit line; and
a control circuit for controlling the operations of the memory circuit;
wherein when testing the memory unit, the control circuit first initiates the memory unit by using the word line connected to the memory unit, and then uses the writing unit connected to the memory unit to write a predetermined binary data bit into the memory unit through one output port of the writing unit connected to the memory unit and the bit line switch and bit line connected between the output port of the writing unit and the memory unit, and then switches off the bit line switch to disconnect the bit line connected to the output port of the writing unit, and finally using the testing unit connected to the output port and the disconnected bit line to test if the binary data bit outputted from the memory unit to the disconnected bit line is the same as the binary data bit outputted from the output port.
It is an advantage of the present invention that the testing method of the memory tests all bits on one word line at one time, and it is not necessary to read out the data written in the memory for testing. Therefore, testing of the memory is more efficient, and the production costs of the memory is reduced. Also, a test machine is not required when testing the memory.
These and other objects and the advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
REFERENCES:
patent: 4680762 (1987-07-01), Hardee et al.
patent: 5400281 (1995-03-01), Morigami
patent: 5428574 (1995-06-01), Kuo et al.
patent: 5638323 (1997-06-01), Itano
Tu Christine T.
United Microelectronics Corp.
Winston Hsu
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