DRAM circuit and method of controlling the same

Details DRAM circuit and method of controlling the same DRAM circuit and method of controlling the same

2001-02-19

2002-09-17

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S205000, C365S189060

Reexamination Certificate

active

06452832

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a Dynamic Random Access Memory (hereinafter referred to as DRAM) circuit and a method of controlling the same, more particularly to achieving a high speed write operation accompanied with a write masking operation for the DRAM circuit. Note that the write masking operation means that a part of data is not written during a write operation, that is, the part of the data is masked.
FIG. 1
is a circuit diagram showing a conventional DRAM circuit. The circuit shown in
FIG. 1
comprises a memory cell array
1
, a group of bit line pairs
2
, a group of sense amplifiers (S/A)
3
, a group of column switches
4
, a group of data line pairs
5
and column select lines
6
. Each sense amplifier
3
is connected to corresponding one of the bit line pairs (BL,/BL)
2
and to corresponding one of the column switches
4
composed of a pair of N-channel FETs (hereinafter referred to as NFETs). Each column switch
4
is connected to corresponding one of data line pairs (DL,/DL)
5
. The four column switches
4
are connected to one column select line
6
. The four column switches
4
are controlled so as to be turned ON/OFF depending on a level (High, Low) of a signal on the column select line
6
. The turning ON of the column switch
4
allows the bit line pair
2
to be electrically connected to the corresponding data line pair
5
via the sense amplifier
3
.
In the write operation of the DRAM circuit shown in
FIG. 1
, the bit line pair
2
is first amplified by the sense amplifier
3
sufficiently. Thereafter, the previously decided four column switches
4
are turned ON by a high level signal on the column select line
6
. As a result, the four bit line pairs
2
are connected to the corresponding data line pairs
5
. At the same time, write data (potential) of each data line pair
5
is inputted to corresponding one of the sense amplifiers
3
, and thus data (potential) on the bit line pair
2
is made to be inverted.
The write masking operation is performed simultaneously with the write operation. When the write masking operation is performed, a selected data line
2
is clamped to be high in level similarly to a read operation. Thereafter, the previously decided four column switches
4
are turned ON by a high level signal on the column select line
6
, and thus the operation is finished.
In a state where the four column switches
4
are turned ON, if the bit line pair
2
is not in a sufficiently amplified condition by the sense amplifier
3
, the sense amplifier
3
malfunctions due to a load of the data line pair, that is, a high potential, so that data on the bit line pair
2
may be destroyed. To prevent the data from being destroyed by the malfunction of the sense amplifier
3
, the column switch
4
must be turned ON after the bit line pair
2
has been sufficiently amplified by the sense amplifier
3
. However, as a result of this, there is a problem that the write operation accompanied with the write masking operation takes more time than a write operation accompanied with no write masking operation. In other words, there is a problem that it is impossible to achieve a high speed write operation in the DRAM circuit. Note that in the case of the write operation accompanied with no write masking operation, generally, it does not matter even if the column switch
5
is turned ON before the bit line pair
2
is sufficiently amplified by the sense amplifier
3
. The reason is that because the write operation rewrites data of the bit line pair
2
, no problem occurs even if the data before rewriting is destroyed.
BRIEF SUMMARY OF THE INVENTION
The object of the present invention is to solve the foregoing problems. Specifically, the object of the present invention is to provide a DRAM circuit of achieving a high speed write operation even when the write operation is accompanied with a write masking operation and a method of controlling the DRAM circuit.
According to the present invention, a DRAM circuit including novel column switches is provided. The novel column switches are controlled by a signal on a data line pair. In other words, the column switches are controlled in accordance with a potential state of the signal on the data line pair. Furthermore, the novel column switches have a function to separate a selected data line pair from a bit line pair corresponding thereto during a write masking operation.


REFERENCES:
patent: 5566128 (1996-10-01), Magome
patent: 6122217 (2000-09-01), Keeth et al.
patent: 6212110 (2001-04-01), Sakamoto et al.

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