DRAM cells with buried trench capacitors

Details DRAM cells with buried trench capacitors DRAM cells with buried trench capacitors

2002-01-23

2002-12-03

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S304000

Reexamination Certificate

active

06489646

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) process, and more particularly, to a process for manufacturing a dynamic random access memory device with buried trench capacitors.
2. Description of the Prior Art
Dynamic random access memory (DRAM) is a type of volatile memory having a signal which is stored in a digital state depending on the charging state of the capacitor in each memory cell. A DRAM memory unit comprises an access transistor and a storage capacitor. The source terminal of the access transistor is connected to the storage electrode, known as the upper electrode, of a storage capacitor. The lower electrode of the storage capacitor is connected to a fixed voltage source. Between the upper electrode and the lower electrode is a dielectric thin film.
A capacitor is at the “heart” of a DRAM storage device. When the amount of electric charges capable of being stored in the capacitor is large, soft errors produced by a particles can be greatly lowered. Furthermore, a large charge storage capacity in the DRAM capacitor is able to lower its refreshing frequency. When a small charge storage capacity is needed in a DRAM capacitor, a conventional two-dimensional or planar type of capacitor can be fabricated in the integrated circuit. However, a planar type capacitor occupies a rather large surface area on the semiconductor substrate surface, hence is not suitable for high integration. Therefore, three-dimensional capacitors, for example, the so-called stacked type or trench type capacitors, are used for increasing the level of integration of DRAMs.
FIGS. 1A through 1L
are schematic cross-sectional views showing the progression of manufacturing steps in the fabrication of an array of trench-type DRAM cells according to a conventional method. As shown in FIG.
1
A and
FIG. 2A
, wherein
FIG. 2A
is a top view for illustrating the following steps and
FIG. 1A
is a cross-sectional view along line I—I of
FIG. 2A
, a pad oxide layer
101
and a silicon nitride layer
102
are sequentially formed on a P type silicon substrate
100
. Then, a plurality of rows of trenches
103
are formed in the P type silicon substrate
100
by patterning the silicon nitride layer
102
and the pad oxide layer
101
with a conventional photolithography and etching method. As shown in
FIG. 2A
, the silicon nitride layer
102
and the pad oxide layer
101
are patterned in the way such that each pair of neighboring trenches
103
in each row of the trenches
103
is separated from each other for a predetermined distance.
Referring next to
FIG. 1B
, a conformal silicon nitride layer
104
is deposited on the P type silicon substrate
100
, and then a sacrificial layer
105
is formed on the conformal silicon nitride layer
104
. Referring to
FIG. 1C
, the sacrificial layer
105
is partially etched away such that the depth of the left sacrificial layer
105
is under the surface of the pad oxide layer
101
, and a portion of the conformal silicon nitride layer
104
in the trench
103
is exposed. Then, referring to
FIG. 1D
, the portion of the conformal silicon nitride layer
104
uncovered by the left sacrificial layer
105
is etched away. Afterward, the left sacrificial layer
105
is removed.
Referring to
FIG. 1E
, a collar oxide layer
106
is then formed around inner sidewalls of each trench
103
uncovered by the left conformal silicon nitride layer
104
by thermal oxidation. Thereafter, the left conformal silicon nitride layer
104
is removed with hot H
3
PO
4
aqueous solution. Subsequently, referring to
FIG. 1F
, an N type diffusion region
107
is formed around the surrounding of each trench
103
in the silicon substrate
100
, using thermal diffusion with N type impurity gas to dope the silicon substrate
100
. The N type diffusion region
107
is used as a bottom electrode of the buried trench capacitor. The regions of the silicon substrate
100
covered by the collar oxide layer
106
are not doped.
Referring next to
FIG. 1G
, a silicon nitride/silicon dioxide (NO) composite layer
108
is formed around the inner peripheral area of each trench
103
uncovered by the collar oxide layer
106
for serving as a dielectric layer of a buried trench capacitor which will be formed later. Referring to
FIG. 1H
, depositing an N type doped polysilicon layer
109
on the silicon substrate
100
to fill each trench
103
and serve as the top electrode of the buried trench capacitor. The N type doped polysilicon layer
109
is partially etched to expose a part of the collar oxide layer
106
in the trench
103
. Referring to
FIG. 11
, etching the exposed part of the collar oxide layer
106
until the surface of the N type doped polysilicon layer
109
.
Referring to
FIG. 1J
, subsequently, depositing an amorphous silicon layer on the silicon substrate
100
, and partially etching the amorphous silicon layer so that the left amorphous silicon layer forms a buried silicon strap
110
in the trench
103
. The buried silicon strap
110
is then doped with N type dopants by ion implantation. An annealing step is performed so that the impanted N type dopants in the buried silicon strap
110
are out diffused to the silicon substrate
100
. The N type doped buried silicon strap
110
electrically couples the top electrode of the buried trench capacitor and a source/drain region of an access transistor on the silicon substrate
100
, which will be formed later. In accordance with the above steps, the buried trench capacitors are completed.
Referring to
FIGS. 1K and 2B
, wherein
FIG. 2B
is a top view for illustrating the following steps and
FIG. 1K
is a cross-sectional view along line II—II of
FIG. 2B
, defining active areas for source/drain regions of the access transistors of the DRAM cells using an island type pattern
111
. As a result, a trench isolation region
112
is formed in the silicon substrate
100
, passing through the respective buried silicon strap
110
and a part of the respective buried trench capacitor, and between the pair of neighboring buried trench capacitors.
Referring to
FIGS. 1L and 2C
, wherein
FIG. 2C
is a top view for illustrating the following steps and
FIG. 1L
is a cross-sectional view along line III—III of
FIG. 2
, an oxide layer is deposited on the silicon substrate
100
to fill the trench isolation region
112
, and then planarized by a chemical mechanical polishing process. At the chemical mechanical polishing process, the silicon nitride layer
102
and the pad oxide layer
101
are removed. Thereafter, an N well is formed in the silicon substrate
100
by ion implantation. The N well electrically couples the bottom electrode of the buried trench capacitor formed of the N type diffusion region
107
to a positive voltage bias. A gate oxide layer
114
is formed on the silicon substrate
100
by thermal oxidation. Then, a gate layer
115
serving as word lines of the DRAM cells are formed by depositing and patterning an N type doped polysilicon layer and a tungsten silicide layer. Then, the source/drain regions
116
of the access transistors are formed by ion implantation. As a consequence, the trench type DRAM cells are completed.
However, in accordance with the conventional process of manufacturing the trench type DRAM cells, the trench capacitor becomes a major limited factor in device scaling. To keep capacitance unchanged, the trench of the trench capacitor must be etched deeper to compensate capacitor area loss from horizontal scaling. It becomes very difficult and costly to etch the trench as the aspect ratio of the trench increases larger. On the other hand, because the trench capacitor is formed before other devices, increasing unit capacitance by reducing the effective dielectric thickness of the trench capacitor seems to be very difficult due to limited high dielectric materials that can sustain high temperature are available.
Accordingly, it is a need to provide an improved process for manufacturing a trench type DRAM cell, which can increase capacitanc

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