DRAM cell with stacked capacitor self-aligned to bitline

Details DRAM cell with stacked capacitor self-aligned to bitline DRAM cell with stacked capacitor self-aligned to bitline

1996-07-30

2002-08-06

Ngô, Ngân V. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S309000

Reexamination Certificate

active

06429473

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to stacked capacitors for integrated circuit chips. More particularly, it relates to a DRAM cell structure and a method for fabrication thereof in which a stacked capacitor is self-aligned to the underlying bitline.
BACKGROUND OF THE INVENTION
Stacked capacitors have been extensively used for charge storage in high density DRAM cells. One type of stacked capacitor is a stud stacked capacitor in which a polysilicon stud is defined, coated with dielectric, and then the dielectric is coated with a conformal layer of polysilicon. Other stacked capacitors have multiple planar layers or vertical cylinders of polysilicon separated by oxide. While stacked capacitors provide advantages for DRAM cells they suffer from several problems. First, there is the problem of overlay mismatch between capacitor plate and node diffusion which can lead to high contact resistance. Second, stacked capacitors have very uneven topography in the array region, making subsequent processing steps, such as photolithography difficult. Third, contact between bitline and bitline diffusion through thick oxide encapsulating the stacked capacitor is difficult. Fourth, photolithographic misalignment of the stacked capacitor to underlying structures contributes to chip to chip variation of the size and capacitance of the stacked capacitor. Fifth, the vertical dimension of the stacked capacitor is limited by the ability to tolerate the topology it contributes and the planar area of the stacked capacitor is limited by the dimensions of the cell. Finally, stacked capacitors pose the need for additional masks to provide the node and bitline contacts.
Thus, a better solution is needed that provides improved overlay between capacitor plate and node diffusion, improved overlay between capacitor plate and bitline, simplified contact to bitline and node diffusions, the ability to extend more vertically while retaining smooth topology, less variation in capacitance among cells, better use of cell area, and all without additional masks. This solution is provided by the following invention.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a DRAM cell stacked capacitor self-aligned to a bitline
It is another object of the present invention to provide a DRAM chip having uniform topology in array and supports circuits portions of the chip to facilitate processing of subsequent wiring levels.
It is another object of the present invention to provide a stacked capacitor occupying nearly all of the area of a cell.
It is a feature of the present invention that portions of a single level of metallization are patterned in separate masking steps.
It is an advantage of the present invention that the stacked capacitor can occupy substantially all the area of a cell except that taken by isolation having a dimension substantially less than the minimum dimension of the photolithographic system used in the fabrication process.
These and other objects, features, and advantages of the invention are accomplished by a method of forming a connector, comprising the steps of: depositing a conductive layer; patterning at least portions of the conductive layer; forming an insulating layer on the conductive layer; and patterning at least portions of the insulating layer and the conductive layer.
Another aspect of the invention is a DRAM cell structure, comprising a stacked capacitor self-aligned to a bitline.


REFERENCES:
patent: 4826781 (1989-05-01), Asahini et al.
patent: 5001526 (1991-03-01), Gotou
patent: 5155056 (1992-10-01), Jeong-Gyoo
patent: 5236855 (1993-08-01), Dennison et al.
patent: 5236860 (1993-08-01), Fazan et al.
patent: 5240871 (1993-08-01), Doan et al.
patent: 5262343 (1993-11-01), Rhodes et al.
patent: 5262662 (1993-11-01), Gonzales et al.
patent: 5266513 (1993-11-01), Fazan et al.
patent: 5292677 (1994-03-01), Dennison
patent: 5629539 (1997-05-01), Aoki et al.
patent: 5663585 (1997-09-01), Lee et al.
patent: 5804853 (1998-09-01), Cronin et al.
patent: 5856704 (1999-01-01), Schuele
patent: 5864156 (1999-01-01), Juengling
patent: 5955758 (1999-09-01), Sandhu et al.
patent: 1306072 (1992-08-01), None
IBM Technical Disclosure Bulletin, vol. 23, No. 12, May 1981, pp. 5346&5347 Title: Hole Opening in Polysilicon by Selective Doping and Removal Technique.

Affiliated with

Also associated with

Rating

DRAM cell with stacked capacitor self-aligned to bitline does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM cell with stacked capacitor self-aligned to bitline, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM cell with stacked capacitor self-aligned to bitline will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2937477