DRAM cell with high integration density

Details DRAM cell with high integration density DRAM cell with high integration density

2002-01-09

2003-03-18

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000

Reexamination Certificate

active

06534811

ABSTRACT:

FIELD OF THE INVENTION
The present invention concerns a process for manufacturing a Dynamic Random Access Memory (DRAM) cell, with a view to improve its integration capacitance. The invention is therefore, more particularly, related to the field of DRAM cell architecture.
BACKGROUND OF THE INVENTION
Each DRAM cell comprises a capacitor of a MOS-type transistor structure and is affected by leakages like any capacitor. Thus, the information contained in each cell containing a binary “1” must be periodically regenerated so it does not disappear.
At the present time, DRAM cells are subject to a greater desire for improved integration. Attempts are thereby being made to increase the number of memory cells manufactured per surface unit in the substrate of a monolithic integrated circuit. In the desire for higher integration density, two prevailing DRAM cell architectures may be distinguished.
First, the most common architecture for manufacturers of semiconductors concerns cells where the capacitor is buried under the transistor. The capacitor is therefore initially formed in a trench in the semiconductor and the transistor is manufactured after the capacitor. The desire to improve integration density is leading to the use of smaller and smaller components, which means that the capacitor aspect ratio must be increased to retain a constant surface and thus a capacitor of equivalent charge.
Indeed, the quantity of charge stored in a capacitor is proportionate to the capacitor surface. So, in the prior art “in-trench” architecture where the capacitor is buried under the transistor, the only way to increase the capacitor surface, and therefore the quantity of stored charges, is to increase the depth of the capacitor. Capacitor surface gain is therefore achieved in the trench.
The main drawback of this architecture is the capacitor aspect ratio of the memory cell structure when the objective is to increase integration density and when, consequently, smaller and smaller components are used. Particularly, in the case of high density integration, where transistors in 0.1 &mgr;m (micrometer) technology are used, the trench depths necessary to retain total equivalent capacitance of 30 fF (femto-Farrad), i.e. the capacitance necessary for the cell to operate correctly, exceeds ten micrometers. This gives a ratio of 100 relative to the transistor size.
Such a trench depth creates a real technological barrier. Uniform etching over several micrometers is indeed extremely difficult to achieve. The complexity of the technological stages to be implemented is therefore a hinderance to improving integration density in architecture where the capacitor is buried.
Moreover, the type of architecture where the capacitor is buried under the transistor does not allow high permittivity dielectric materials, such as tantalum pentoxide Ta
2
O
5
for example, to be integrated into the capacitor. Indeed, since the capacitor is formed before the transistor is manufactured, the anneal stage, which allows the impurities of the source and drain zones of the transistor to be activated, causes severe degradation of the dielectric properties of the tantalum pentoxide. The thermal balance of the transistor therefore prevents the integration of high permittivity dielectrics into this type of architecture.
A second type of known architecture concerns the so-called “superposed” cells, where the capacitor is formed after the transistor.
FIG. 1
shows such a DRAM cell architecture where a capacitor
1
is formed above a transistor
2
. The transistor
2
includes a gate
2
g
and a source and drain zone,
2
s
and
2
d
respectively. The contact between the transistor
2
and the capacitor
1
operates through a contact point of the capacitor
3
. Another contact point
4
allows contact between a first bit line
5
and the transistor
2
. Thus, when the gate
2
g
is energized, i.e. when the transistor is conducting, the current brought by the contact point
4
passes through the source and drain zones
2
s
and
2
d
and charges the capacitor.
In this architecture, when attempting to increase integration density, achieving the contact
4
to the bit line
5
becomes problematic. Indeed, the capacitor
1
must be integrated under the metallization line while retaining a separation of F relative to the contact point
4
. Thus, when using photolithography to define the contacts, a minimum distance must be observed between the capacitor and the contact point.
This constraint limits the size of the cell to a minimum length in the event a surface with a sufficient capacitance is required. In the ideal case where the length of the cell is reduced to 4F, for example in
FIG. 1
, the contacts
3
of the capacitors must be self-aligned with the transistors. The technology using self-aligned contacts is extremely complex, difficult to control and therefore expensive.
Thus, in the “superposed” type architecture, the aspect ratio of the capacitor is still dominant. In addition, despite the use of high permittivity dielectrics, the constraints on achieving good integration density are significant. In particular, this is so regarding the margins to be observed during the photolithography for making the capacitor contact. The architecture is therefore limited by its spatial requirement. Even when the capacitor is made after the transistor and therefore not subjected to an anneal stage, the architecture allows materials with high dielectric constants, such as tantalum pentoxide, to replace silicon dioxide as the capacitor dielectric.
SUMMARY OF THE INVENTION
The object of the invention is to provide a DRAM cell architecture which remains compatible with the use of high permittivity dielectrics for the capacitor and which allows integration density, i.e. the number of cells on a given surface, to be increased or optimized while overcoming the technological problems restricting the integration of prior art architectures. To this end, the DRAM cell architecture of the invention allows a lateral development of the capacitor, thus offering a significant surface gain which restricts the aspect ratio relative to the cell size.
To do this, the invention proposes an architecture where the capacitor may be of the buried-type. Therefore, there are no alignment problems with the contacts. However, the capacitor is made after the transistor, unlike prior art architectures of this type. This characteristic thus allows high permittivity insulating materials to be integrated to form the capacitor dielectric.
The DRAM cell structure according to the invention is therefore distinguished by a capacitor formed in a trench after making the transistor and, moreover, providing lateral surface development in the silicon substrate. The particular in-trench capacitor structure therefore requires appreciably shallower in-trench lithography than the in-trench structure of the prior art to obtain the required capacitor surface.
Advantageously, the capacitor lateral development is implemented by using etch selectivity between silicon germanium (SiGe) and silicon (Si). The present invention thus implements the principle of “Silicon On Nothing” (SON) technology, developed in French Patent No. 9,903,470 to which the reader may refer for more information. This technology was developed to isolate a transistor from the substrate by an isolator, but has never been applied to forming a capacitor in a DRAM cell.
The invention therefore is directed to a process for making a DRAM cell comprising: growing silicon germanium layers and silicon layers, by epitaxy, from a silicon substrate; superposing a first N+ doped silicon layer and a second P doped silicon layer; forming a transistor on the obtained substrate, the transistor comprising a gate, a source zone, a drain zone, spacers and a hard mask to cover the gate of the transistor; etching a trench in the extension of the transistor to provide access to the silicon germanium layers; selectively etching the silicon germanium layers over a pre-set depth relative to the silicon layers to form lateral cavities; and forming a cap

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