DRAM cell with enhanced SER immunity

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Reexamination Certificate

active

06888187

ABSTRACT:
A memory cell that has first and second fully depleted transfer devices each having a body region and first and second diffused electrodes. The cell has a differential storage capacitor having at least one node abutting and in electrical contact with one of the first and second diffused electrodes of each of the transfer devices. The storage capacitor has a primary capacitance and a plurality of inherent capacitances, wherein the primary capacitance has a capaictive value that is at least approximately five times greater than that of the plurality of inherent capacitances.

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Choi Y.K. et al. “30 nm ultra-thin-body SOI MOSFET with selective deposied Ge raised S/D”, Jun. 2000. 58th Dev Res Conf (DRC). pp. 23-24.

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