DRAM cell with a roughened poly-Si electrode

Semiconductor device manufacturing: process – Making passive device – Stacked capacitor

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Details

438253, 438255, 438396, 438960, 438964, H01L 218242

Patent

active

059703601

ABSTRACT:
A porous silicon layer is created by using wet etching to etch a polysilicon layer. In preferred embodiment, the polysilicon layer is treated by H.sub.3 PO.sub.4 solution at 60-165.degree. C. for about 3-200 minutes. The porous silicon layer is subsequently treated by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes to form a roughened polysilicon layer. The SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O. The volume ratio for the three compounds of said SC-1 is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20. The next step of the formation is the deposition of a dielectric film along the roughened surface of the micro-islands polysilicon layers. A conductive layer is deposited over the dielectric film. Next, photolithgraphy and etching process are used to etch the conductive layer, the dielectric film and the micro-islands polysilicon layer into a portion of the layer.

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